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tilelink2: improve round robin arbiter QoR

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This commit is contained in:
Wesley W. Terpstra 2017-06-01 15:26:04 -07:00
parent 5994714970
commit 1f531b1593
2 changed files with 13 additions and 10 deletions
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4
src/main/scala/uncore/tilelink2/Arbiter.scala
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@ -13,12 +13,12 @@ object TLArbiter
val lowestIndexFirst: Policy = (width, valids, select) => ~(leftOR(valids) << 1)(width-1, 0) val lowestIndexFirst: Policy = (width, valids, select) => ~(leftOR(valids) << 1)(width-1, 0)
val roundRobin: Policy = (width, valids, select) => { val roundRobin: Policy = (width, valids, select) => if (width == 1) UInt(1, width=1) else {
val valid = valids(width-1, 0) val valid = valids(width-1, 0)
assert (valid === valids) assert (valid === valids)
val mask = RegInit(~UInt(0, width=width)) val mask = RegInit(~UInt(0, width=width))
val filter = Cat(valid & ~mask, valid) val filter = Cat(valid & ~mask, valid)
val unready = (rightOR(filter, width*2) >> 1) | (mask << width) // last right shift unneeded val unready = (rightOR(filter, width*2, width) >> 1) | (mask << width)
val readys = ~((unready >> width) & unready(width-1, 0)) val readys = ~((unready >> width) & unready(width-1, 0))
when (select && valid.orR) { when (select && valid.orR) {
mask := leftOR(readys & valid, width) mask := leftOR(readys & valid, width)

19
src/main/scala/uncore/tilelink2/package.scala
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@ -5,6 +5,7 @@ package uncore
import Chisel._ import Chisel._
import diplomacy._ import diplomacy._
import util._ import util._
import scala.math.min
package object tilelink2 package object tilelink2
{ {
@ -19,18 +20,20 @@ package object tilelink2
def UIntToOH1(x: UInt, width: Int) = ~(SInt(-1, width=width).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt, width: Int) = ~(SInt(-1, width=width).asUInt << x)(width-1, 0)
def trailingZeros(x: Int) = if (x > 0) Some(log2Ceil(x & -x)) else None def trailingZeros(x: Int) = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits // Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth) def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, w: Integer): UInt = { def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt = def helper(s: Int, x: UInt): UInt =
if (s >= w) x else helper(s+s, x | (x << s)(w-1,0)) if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(w-1, 0) helper(1, x)(width-1, 0)
} }
// Fill 1s form high bits to low bits // Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth) def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, w: Integer): UInt = { def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt = def helper(s: Int, x: UInt): UInt =
if (s >= w) x else helper(s+s, x | (x >> s)) if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(w-1, 0) helper(1, x)(width-1, 0)
} }
// This gets used everywhere, so make the smallest circuit possible ... // This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size // Given an address and size, create a mask of beatBytes size