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tilelink: RAMModel support early reuse of source

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This commit is contained in:
Wesley W. Terpstra 2017-07-26 10:50:47 -07:00
parent 138276fd87
commit 1efdca106c
1 changed files with 1 additions and 1 deletions
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src/main/scala/tilelink/RAMModel.scala
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@ -95,7 +95,7 @@ class TLRAMModel(log: String = "")(implicit p: Parameters) extends LazyModule
when (in.a.fire()) { flight(in.a.bits.source) := a_flight } when (in.a.fire()) { flight(in.a.bits.source) := a_flight }
val bypass = if (edge.manager.minLatency > 0) Bool(false) else in.a.valid && in.a.bits.source === out.d.bits.source val bypass = if (edge.manager.minLatency > 0) Bool(false) else in.a.valid && in.a.bits.source === out.d.bits.source
val d_flight = RegNext(Mux(bypass, a_flight, flight(out.d.bits.source))) val d_flight = RegEnable(Mux(bypass, a_flight, flight(out.d.bits.source)), edge.first(out.d))
// Process A access requests // Process A access requests
val a = Reg(next = in.a.bits) val a = Reg(next = in.a.bits)