From 1efdca106c057aa0a152500030fac435091022b2 Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Wed, 26 Jul 2017 10:50:47 -0700 Subject: [PATCH] tilelink: RAMModel support early reuse of source --- src/main/scala/tilelink/RAMModel.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/tilelink/RAMModel.scala b/src/main/scala/tilelink/RAMModel.scala index 6fb138a3..88f8cc38 100644 --- a/src/main/scala/tilelink/RAMModel.scala +++ b/src/main/scala/tilelink/RAMModel.scala @@ -95,7 +95,7 @@ class TLRAMModel(log: String = "")(implicit p: Parameters) extends LazyModule when (in.a.fire()) { flight(in.a.bits.source) := a_flight } val bypass = if (edge.manager.minLatency > 0) Bool(false) else in.a.valid && in.a.bits.source === out.d.bits.source - val d_flight = RegNext(Mux(bypass, a_flight, flight(out.d.bits.source))) + val d_flight = RegEnable(Mux(bypass, a_flight, flight(out.d.bits.source)), edge.first(out.d)) // Process A access requests val a = Reg(next = in.a.bits)