riscv/rocket-chip
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rocketchip: don't waste too many sources on the AXI master port

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This commit is contained in:
Wesley W. Terpstra 2016-11-22 21:48:41 -08:00
parent c0b27999ea
commit 1e7d597fd3
1 changed files with 5 additions and 3 deletions
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8
src/main/scala/rocketchip/Periphery.scala
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@ -155,12 +155,14 @@ trait PeripheryMasterAXI4MMIOModule {
// PeripherySlaveAXI4 is an example, make your own cake pattern like this one. // PeripherySlaveAXI4 is an example, make your own cake pattern like this one.
trait PeripherySlaveAXI4 extends L2Crossbar { trait PeripherySlaveAXI4 extends L2Crossbar {
private val idBits = 8 private val axiIdBits = 8
private val tlIdBits = 2 // at most 4 AXI requets inflight at a time
val l2_axi4 = AXI4BlindInputNode(AXI4MasterPortParameters( val l2_axi4 = AXI4BlindInputNode(AXI4MasterPortParameters(
masters = Seq(AXI4MasterParameters( masters = Seq(AXI4MasterParameters(
id = IdRange(0, 1 << idBits))))) id = IdRange(0, 1 << axiIdBits)))))
l2.node := AXI4ToTL()(AXI4Fragmenter()(l2_axi4)) l2.node := TLSourceShrinker(1 << tlIdBits)(AXI4ToTL()(AXI4Fragmenter()(l2_axi4)))
} }
trait PeripherySlaveAXI4Bundle extends L2CrossbarBundle { trait PeripherySlaveAXI4Bundle extends L2CrossbarBundle {