From 1e7d597fd37063710a66a79a4c9f0e05d73c5c4f Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Tue, 22 Nov 2016 21:48:41 -0800 Subject: [PATCH] rocketchip: don't waste too many sources on the AXI master port --- src/main/scala/rocketchip/Periphery.scala | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/src/main/scala/rocketchip/Periphery.scala b/src/main/scala/rocketchip/Periphery.scala index 9458e328..35d5306f 100644 --- a/src/main/scala/rocketchip/Periphery.scala +++ b/src/main/scala/rocketchip/Periphery.scala @@ -155,12 +155,14 @@ trait PeripheryMasterAXI4MMIOModule { // PeripherySlaveAXI4 is an example, make your own cake pattern like this one. trait PeripherySlaveAXI4 extends L2Crossbar { - private val idBits = 8 + private val axiIdBits = 8 + private val tlIdBits = 2 // at most 4 AXI requets inflight at a time + val l2_axi4 = AXI4BlindInputNode(AXI4MasterPortParameters( masters = Seq(AXI4MasterParameters( - id = IdRange(0, 1 << idBits))))) + id = IdRange(0, 1 << axiIdBits))))) - l2.node := AXI4ToTL()(AXI4Fragmenter()(l2_axi4)) + l2.node := TLSourceShrinker(1 << tlIdBits)(AXI4ToTL()(AXI4Fragmenter()(l2_axi4))) } trait PeripherySlaveAXI4Bundle extends L2CrossbarBundle {