[tilelink2] allow TL monitors to be globally enabled or disabled (#392)
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		@@ -17,6 +17,8 @@ import coreplex._
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case object GlobalAddrMap extends Field[AddrMap]
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					case object GlobalAddrMap extends Field[AddrMap]
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case object ConfigString extends Field[String]
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					case object ConfigString extends Field[String]
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case object NCoreplexExtClients extends Field[Int]
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					case object NCoreplexExtClients extends Field[Int]
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					/** Enable or disable monitoring of Diplomatic buses */
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					case object TLEmitMonitors extends Field[Bool]
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/** Function for building Coreplex */
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					/** Function for building Coreplex */
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case object BuildCoreplex extends Field[(CoreplexConfig, Parameters) => BaseCoreplexModule[BaseCoreplex, BaseCoreplexBundle]]
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					case object BuildCoreplex extends Field[(CoreplexConfig, Parameters) => BaseCoreplexModule[BaseCoreplex, BaseCoreplexBundle]]
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@@ -27,6 +29,8 @@ abstract class BaseTop(q: Parameters) extends LazyModule {
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  val pBusMasters = new RangeManager
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					  val pBusMasters = new RangeManager
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  val pDevices = new ResourceManager[AddrMapEntry]
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					  val pDevices = new ResourceManager[AddrMapEntry]
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					  TLImp.emitMonitors = q(TLEmitMonitors)
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  // Add a peripheral bus
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					  // Add a peripheral bus
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  val peripheryBus = LazyModule(new TLXbar)
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					  val peripheryBus = LazyModule(new TLXbar)
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  lazy val peripheryManagers = peripheryBus.node.edgesIn(0).manager.managers
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					  lazy val peripheryManagers = peripheryBus.node.edgesIn(0).manager.managers
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@@ -33,6 +33,7 @@ class BasePlatformConfig extends Config(
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          dataBits = edgeDataBits,
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					          dataBits = edgeDataBits,
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          addrBits = site(PAddrBits),
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					          addrBits = site(PAddrBits),
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          idBits = site(EdgeIDBits))
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					          idBits = site(EdgeIDBits))
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					        case TLEmitMonitors => true
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        case TLKey("EdgetoSlave") =>
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					        case TLKey("EdgetoSlave") =>
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          site(TLKey("L1toL2")).copy(dataBeats = edgeDataBeats)
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					          site(TLKey("L1toL2")).copy(dataBeats = edgeDataBeats)
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        case TLKey("MCtoEdge") =>
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					        case TLKey("MCtoEdge") =>
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@@ -201,3 +202,17 @@ class With64BitPeriphery extends Config (
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    case PeripheryBusKey => PeripheryBusConfig(arithAMO = true, beatBytes = 8)
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					    case PeripheryBusKey => PeripheryBusConfig(arithAMO = true, beatBytes = 8)
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  }
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					  }
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)
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					)
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					class WithTLMonitors extends Config (
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					  (pname, site, here) => pname match {
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					    case TLEmitMonitors => true
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					    case _ => throw new CDEMatchError
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					  }
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					)
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					class WithoutTLMonitors extends Config (
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					  (pname, site, here) => pname match {
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					    case TLEmitMonitors => false
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					    case _ => throw new CDEMatchError
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					  }
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					)
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@@ -20,12 +20,17 @@ object TLImp extends NodeImp[TLClientPortParameters, TLManagerPortParameters, TL
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    Vec(ei.size, TLBundle(ei.map(_.bundle).reduce(_.union(_)))).flip
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					    Vec(ei.size, TLBundle(ei.map(_.bundle).reduce(_.union(_)))).flip
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  }
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					  }
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					  var emitMonitors = true
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  def colour = "#000000" // black
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					  def colour = "#000000" // black
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  def connect(bo: => TLBundle, bi: => TLBundle, ei: => TLEdgeIn)(implicit sourceInfo: SourceInfo): (Option[LazyModule], () => Unit) = {
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					  def connect(bo: => TLBundle, bi: => TLBundle, ei: => TLEdgeIn)(implicit sourceInfo: SourceInfo): (Option[LazyModule], () => Unit) = {
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    val monitor = LazyModule(new TLMonitor(() => new TLBundleSnoop(bo.params), () => ei, sourceInfo))
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					    val monitor = if (emitMonitors) {
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    (Some(monitor), () => {
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					      Some(LazyModule(new TLMonitor(() => new TLBundleSnoop(bo.params), () => ei, sourceInfo)))
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					    } else {
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					      None
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					    }
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					    (monitor, () => {
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      bi <> bo
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					      bi <> bo
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      monitor.module.io.in := TLBundleSnoop(bo)
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					      monitor.foreach { _.module.io.in := TLBundleSnoop(bo) }
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    })
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					    })
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  }
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					  }
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