From 1e69a2dc1c502767878fff643df5d968e2d03524 Mon Sep 17 00:00:00 2001
From: Henry Cook <henry.m.cook+github@gmail.com>
Date: Sun, 9 Oct 2016 12:34:10 -0700
Subject: [PATCH] [tilelink2] allow TL monitors to be globally enabled or
 disabled (#392)

---
 src/main/scala/rocketchip/BaseTop.scala     |  4 ++++
 src/main/scala/rocketchip/Configs.scala     | 15 +++++++++++++++
 src/main/scala/uncore/tilelink2/Nodes.scala | 11 ++++++++---
 3 files changed, 27 insertions(+), 3 deletions(-)

diff --git a/src/main/scala/rocketchip/BaseTop.scala b/src/main/scala/rocketchip/BaseTop.scala
index 4638be12..159fd159 100644
--- a/src/main/scala/rocketchip/BaseTop.scala
+++ b/src/main/scala/rocketchip/BaseTop.scala
@@ -17,6 +17,8 @@ import coreplex._
 case object GlobalAddrMap extends Field[AddrMap]
 case object ConfigString extends Field[String]
 case object NCoreplexExtClients extends Field[Int]
+/** Enable or disable monitoring of Diplomatic buses */
+case object TLEmitMonitors extends Field[Bool]
 /** Function for building Coreplex */
 case object BuildCoreplex extends Field[(CoreplexConfig, Parameters) => BaseCoreplexModule[BaseCoreplex, BaseCoreplexBundle]]
 
@@ -27,6 +29,8 @@ abstract class BaseTop(q: Parameters) extends LazyModule {
   val pBusMasters = new RangeManager
   val pDevices = new ResourceManager[AddrMapEntry]
 
+  TLImp.emitMonitors = q(TLEmitMonitors)
+
   // Add a peripheral bus
   val peripheryBus = LazyModule(new TLXbar)
   lazy val peripheryManagers = peripheryBus.node.edgesIn(0).manager.managers
diff --git a/src/main/scala/rocketchip/Configs.scala b/src/main/scala/rocketchip/Configs.scala
index 97d9594f..90f48711 100644
--- a/src/main/scala/rocketchip/Configs.scala
+++ b/src/main/scala/rocketchip/Configs.scala
@@ -33,6 +33,7 @@ class BasePlatformConfig extends Config(
           dataBits = edgeDataBits,
           addrBits = site(PAddrBits),
           idBits = site(EdgeIDBits))
+        case TLEmitMonitors => true
         case TLKey("EdgetoSlave") =>
           site(TLKey("L1toL2")).copy(dataBeats = edgeDataBeats)
         case TLKey("MCtoEdge") =>
@@ -201,3 +202,17 @@ class With64BitPeriphery extends Config (
     case PeripheryBusKey => PeripheryBusConfig(arithAMO = true, beatBytes = 8)
   }
 )
+
+class WithTLMonitors extends Config (
+  (pname, site, here) => pname match {
+    case TLEmitMonitors => true
+    case _ => throw new CDEMatchError
+  }
+)
+
+class WithoutTLMonitors extends Config (
+  (pname, site, here) => pname match {
+    case TLEmitMonitors => false
+    case _ => throw new CDEMatchError
+  }
+)
diff --git a/src/main/scala/uncore/tilelink2/Nodes.scala b/src/main/scala/uncore/tilelink2/Nodes.scala
index e92e7445..ffb10476 100644
--- a/src/main/scala/uncore/tilelink2/Nodes.scala
+++ b/src/main/scala/uncore/tilelink2/Nodes.scala
@@ -20,12 +20,17 @@ object TLImp extends NodeImp[TLClientPortParameters, TLManagerPortParameters, TL
     Vec(ei.size, TLBundle(ei.map(_.bundle).reduce(_.union(_)))).flip
   }
 
+  var emitMonitors = true
   def colour = "#000000" // black
   def connect(bo: => TLBundle, bi: => TLBundle, ei: => TLEdgeIn)(implicit sourceInfo: SourceInfo): (Option[LazyModule], () => Unit) = {
-    val monitor = LazyModule(new TLMonitor(() => new TLBundleSnoop(bo.params), () => ei, sourceInfo))
-    (Some(monitor), () => {
+    val monitor = if (emitMonitors) {
+      Some(LazyModule(new TLMonitor(() => new TLBundleSnoop(bo.params), () => ei, sourceInfo)))
+    } else {
+      None
+    }
+    (monitor, () => {
       bi <> bo
-      monitor.module.io.in := TLBundleSnoop(bo)
+      monitor.foreach { _.module.io.in := TLBundleSnoop(bo) }
     })
   }