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[tilelink2] allow TL monitors to be globally enabled or disabled (#392)

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Henry Cook 2016-10-09 12:34:10 -07:00 committed by GitHub
parent 53360f4c2c
commit 1e69a2dc1c
3 changed files with 27 additions and 3 deletions
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4
src/main/scala/rocketchip/BaseTop.scala
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@ -17,6 +17,8 @@ import coreplex._
case object GlobalAddrMap extends Field[AddrMap] case object GlobalAddrMap extends Field[AddrMap]
case object ConfigString extends Field[String] case object ConfigString extends Field[String]
case object NCoreplexExtClients extends Field[Int] case object NCoreplexExtClients extends Field[Int]
/** Enable or disable monitoring of Diplomatic buses */
case object TLEmitMonitors extends Field[Bool]
/** Function for building Coreplex */ /** Function for building Coreplex */
case object BuildCoreplex extends Field[(CoreplexConfig, Parameters) => BaseCoreplexModule[BaseCoreplex, BaseCoreplexBundle]] case object BuildCoreplex extends Field[(CoreplexConfig, Parameters) => BaseCoreplexModule[BaseCoreplex, BaseCoreplexBundle]]
@ -27,6 +29,8 @@ abstract class BaseTop(q: Parameters) extends LazyModule {
val pBusMasters = new RangeManager val pBusMasters = new RangeManager
val pDevices = new ResourceManager[AddrMapEntry] val pDevices = new ResourceManager[AddrMapEntry]
TLImp.emitMonitors = q(TLEmitMonitors)
// Add a peripheral bus // Add a peripheral bus
val peripheryBus = LazyModule(new TLXbar) val peripheryBus = LazyModule(new TLXbar)
lazy val peripheryManagers = peripheryBus.node.edgesIn(0).manager.managers lazy val peripheryManagers = peripheryBus.node.edgesIn(0).manager.managers

15
src/main/scala/rocketchip/Configs.scala
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@ -33,6 +33,7 @@ class BasePlatformConfig extends Config(
dataBits = edgeDataBits, dataBits = edgeDataBits,
addrBits = site(PAddrBits), addrBits = site(PAddrBits),
idBits = site(EdgeIDBits)) idBits = site(EdgeIDBits))
case TLEmitMonitors => true
case TLKey("EdgetoSlave") => case TLKey("EdgetoSlave") =>
site(TLKey("L1toL2")).copy(dataBeats = edgeDataBeats) site(TLKey("L1toL2")).copy(dataBeats = edgeDataBeats)
case TLKey("MCtoEdge") => case TLKey("MCtoEdge") =>
@ -201,3 +202,17 @@ class With64BitPeriphery extends Config (
case PeripheryBusKey => PeripheryBusConfig(arithAMO = true, beatBytes = 8) case PeripheryBusKey => PeripheryBusConfig(arithAMO = true, beatBytes = 8)
} }
) )
class WithTLMonitors extends Config (
(pname, site, here) => pname match {
case TLEmitMonitors => true
case _ => throw new CDEMatchError
}
)
class WithoutTLMonitors extends Config (
(pname, site, here) => pname match {
case TLEmitMonitors => false
case _ => throw new CDEMatchError
}
)

11
src/main/scala/uncore/tilelink2/Nodes.scala
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@ -20,12 +20,17 @@ object TLImp extends NodeImp[TLClientPortParameters, TLManagerPortParameters, TL
Vec(ei.size, TLBundle(ei.map(_.bundle).reduce(_.union(_)))).flip Vec(ei.size, TLBundle(ei.map(_.bundle).reduce(_.union(_)))).flip
} }
var emitMonitors = true
def colour = "#000000" // black def colour = "#000000" // black
def connect(bo: => TLBundle, bi: => TLBundle, ei: => TLEdgeIn)(implicit sourceInfo: SourceInfo): (Option[LazyModule], () => Unit) = { def connect(bo: => TLBundle, bi: => TLBundle, ei: => TLEdgeIn)(implicit sourceInfo: SourceInfo): (Option[LazyModule], () => Unit) = {
val monitor = LazyModule(new TLMonitor(() => new TLBundleSnoop(bo.params), () => ei, sourceInfo)) val monitor = if (emitMonitors) {
(Some(monitor), () => { Some(LazyModule(new TLMonitor(() => new TLBundleSnoop(bo.params), () => ei, sourceInfo)))
} else {
None
}
(monitor, () => {
bi <> bo bi <> bo
monitor.module.io.in := TLBundleSnoop(bo) monitor.foreach { _.module.io.in := TLBundleSnoop(bo) }
}) })
} }