[tilelink2] allow TL monitors to be globally enabled or disabled (#392)

src/main/scala/rocketchip/BaseTop.scala

@@ -17,6 +17,8 @@ import coreplex._
 case object GlobalAddrMap extends Field[AddrMap]
 case object ConfigString extends Field[String]
 case object NCoreplexExtClients extends Field[Int]
+/** Enable or disable monitoring of Diplomatic buses */
+case object TLEmitMonitors extends Field[Bool]
 /** Function for building Coreplex */
 case object BuildCoreplex extends Field[(CoreplexConfig, Parameters) => BaseCoreplexModule[BaseCoreplex, BaseCoreplexBundle]]
 
@@ -27,6 +29,8 @@ abstract class BaseTop(q: Parameters) extends LazyModule {
   val pBusMasters = new RangeManager
   val pDevices = new ResourceManager[AddrMapEntry]
 
+  TLImp.emitMonitors = q(TLEmitMonitors)
+
   // Add a peripheral bus
   val peripheryBus = LazyModule(new TLXbar)
   lazy val peripheryManagers = peripheryBus.node.edgesIn(0).manager.managers

src/main/scala/rocketchip/Configs.scala

@@ -33,6 +33,7 @@ class BasePlatformConfig extends Config(
           dataBits = edgeDataBits,
           addrBits = site(PAddrBits),
           idBits = site(EdgeIDBits))
+        case TLEmitMonitors => true
         case TLKey("EdgetoSlave") =>
           site(TLKey("L1toL2")).copy(dataBeats = edgeDataBeats)
         case TLKey("MCtoEdge") =>
@@ -201,3 +202,17 @@ class With64BitPeriphery extends Config (
     case PeripheryBusKey => PeripheryBusConfig(arithAMO = true, beatBytes = 8)
   }
 )
+
+class WithTLMonitors extends Config (
+  (pname, site, here) => pname match {
+    case TLEmitMonitors => true
+    case _ => throw new CDEMatchError
+  }
+)
+
+class WithoutTLMonitors extends Config (
+  (pname, site, here) => pname match {
+    case TLEmitMonitors => false
+    case _ => throw new CDEMatchError
+  }
+)