riscv/rocket-chip
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flip direction of ioPipe to match ioDecoupled

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This commit is contained in:
Andrew Waterman 2012-03-02 16:18:32 -08:00
parent 7406908d4a
commit 1e1926ce63
3 changed files with 6 additions and 6 deletions
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4
rocket/src/main/scala/coherence.scala
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@ -23,7 +23,7 @@ class ioMem() extends Bundle
{ {
val req_cmd = (new ioDecoupled) { new MemReqCmd() } val req_cmd = (new ioDecoupled) { new MemReqCmd() }
val req_data = (new ioDecoupled) { new MemData() } val req_data = (new ioDecoupled) { new MemData() }
val resp = (new ioPipe) { new MemResp() } val resp = (new ioPipe) { new MemResp() }.flip
} }
class HubMemReq extends Bundle { class HubMemReq extends Bundle {
@ -86,7 +86,7 @@ class ioTileLink extends Bundle {
val probe_req = (new ioDecoupled) { new ProbeRequest() }.flip val probe_req = (new ioDecoupled) { new ProbeRequest() }.flip
val probe_rep = (new ioDecoupled) { new ProbeReply() } val probe_rep = (new ioDecoupled) { new ProbeReply() }
val probe_rep_data = (new ioDecoupled) { new ProbeReplyData() } val probe_rep_data = (new ioDecoupled) { new ProbeReplyData() }
val xact_rep = (new ioPipe) { new TransactionReply() } val xact_rep = (new ioPipe) { new TransactionReply() }.flip
val xact_finish = (new ioDecoupled) { new TransactionFinish() } val xact_finish = (new ioDecoupled) { new TransactionFinish() }
} }

4
rocket/src/main/scala/queues.scala
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@ -66,8 +66,8 @@ object Queue
class pipereg[T <: Data]()(data: => T) extends Component class pipereg[T <: Data]()(data: => T) extends Component
{ {
val io = new Bundle { val io = new Bundle {
val enq = new ioPipe()(data) val enq = new ioPipe()(data).flip
val deq = new ioPipe()(data).flip val deq = new ioPipe()(data)
} }
//val bits = Reg() { io.enq.bits.clone } //val bits = Reg() { io.enq.bits.clone }

4
rocket/src/main/scala/util.scala
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@ -175,8 +175,8 @@ class ioDecoupled[+T <: Data]()(data: => T) extends Bundle
class ioPipe[T <: Data]()(data: => T) extends Bundle class ioPipe[T <: Data]()(data: => T) extends Bundle
{ {
val valid = Bool(INPUT) val valid = Bool(OUTPUT)
val bits = data.asInput val bits = data.asOutput
} }
class ioArbiter[T <: Data](n: Int)(data: => T) extends Bundle { class ioArbiter[T <: Data](n: Int)(data: => T) extends Bundle {