diff --git a/rocket/src/main/scala/coherence.scala b/rocket/src/main/scala/coherence.scala
index 536a4775..195234a4 100644
--- a/rocket/src/main/scala/coherence.scala
+++ b/rocket/src/main/scala/coherence.scala
@@ -23,7 +23,7 @@ class ioMem() extends Bundle
 {
   val req_cmd  = (new ioDecoupled) { new MemReqCmd() }
   val req_data = (new ioDecoupled) { new MemData() }
-  val resp     = (new ioPipe) { new MemResp() }
+  val resp     = (new ioPipe) { new MemResp() }.flip
 }
 
 class HubMemReq extends Bundle {
@@ -86,7 +86,7 @@ class ioTileLink extends Bundle {
   val probe_req      = (new ioDecoupled) { new ProbeRequest() }.flip
   val probe_rep      = (new ioDecoupled) { new ProbeReply() }
   val probe_rep_data = (new ioDecoupled) { new ProbeReplyData() }
-  val xact_rep       = (new ioPipe)     { new TransactionReply() }
+  val xact_rep       = (new ioPipe)      { new TransactionReply() }.flip
   val xact_finish    = (new ioDecoupled) { new TransactionFinish() }
 }
 
diff --git a/rocket/src/main/scala/queues.scala b/rocket/src/main/scala/queues.scala
index 46f1ddec..823a031b 100644
--- a/rocket/src/main/scala/queues.scala
+++ b/rocket/src/main/scala/queues.scala
@@ -66,8 +66,8 @@ object Queue
 class pipereg[T <: Data]()(data: => T) extends Component
 {
   val io = new Bundle {
-    val enq = new ioPipe()(data)
-    val deq = new ioPipe()(data).flip
+    val enq = new ioPipe()(data).flip
+    val deq = new ioPipe()(data)
   }
 
   //val bits = Reg() { io.enq.bits.clone }
diff --git a/rocket/src/main/scala/util.scala b/rocket/src/main/scala/util.scala
index 4b59d022..60225a9e 100644
--- a/rocket/src/main/scala/util.scala
+++ b/rocket/src/main/scala/util.scala
@@ -175,8 +175,8 @@ class ioDecoupled[+T <: Data]()(data: => T) extends Bundle
 
 class ioPipe[T <: Data]()(data: => T) extends Bundle
 {
-  val valid = Bool(INPUT)
-  val bits = data.asInput
+  val valid = Bool(OUTPUT)
+  val bits = data.asOutput
 }
 
 class ioArbiter[T <: Data](n: Int)(data: => T) extends Bundle {