riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

new metadata api

Browse Source
This commit is contained in:
Henry Cook
2015-02-28 17:00:05 -08:00
parent 0b131173e6
commit 1e0c16c557
2 changed files with 61 additions and 52 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
rocket/src/main/scala/icache.scala
View File

@ -7,10 +7,10 @@ import Util._
case object ECCCode extends Field[Option[Code]]
abstract trait L1CacheParameters extends CacheParameters with CoreParameters {
val co = params(TLCoherence)
val code = params(ECCCode).getOrElse(new IdentityCode)
val outerDataBeats = params(TLDataBeats)
val refillCyclesPerBeat = params(TLDataBits)/rowBits
val outerDataBits = params(TLDataBits)
val code = params(ECCCode).getOrElse(new IdentityCode)
val refillCyclesPerBeat = outerDataBits/rowBits
val refillCycles = refillCyclesPerBeat*outerDataBeats
}
@ -273,7 +273,7 @@ class ICache extends FrontendModule
// output signals
io.resp.valid := s2_hit
io.mem.acquire.valid := (state === s_request) && ack_q.io.enq.ready
io.mem.acquire.bits.payload := UncachedReadBlock(addr_block = s2_addr >> UInt(blockOffBits))
io.mem.acquire.bits.payload := GetBlock(addr_block = s2_addr >> UInt(blockOffBits))
io.mem.finish <> ack_q.io.deq
// control state machine