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dcache: the high bit of s2_req.typ is the SIGN bit (not size) (#455)

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Wesley W. Terpstra 2016-11-25 15:26:22 -08:00 committed by GitHub
parent f19d504c88
commit 1e0aca7358
1 changed files with 1 additions and 1 deletions
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src/main/scala/rocket/Dcache.scala
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@ -251,7 +251,7 @@ class DCacheModule(outer: DCache)(implicit p: Parameters) extends HellaCacheModu
val a_source = PriorityEncoder(~uncachedInFlight.asUInt) val a_source = PriorityEncoder(~uncachedInFlight.asUInt)
val acquire_address = s2_req_block_addr val acquire_address = s2_req_block_addr
val access_address = s2_req.addr val access_address = s2_req.addr
val a_size = s2_req.typ val a_size = s2_req.typ(MT_SZ-2, 0)
val a_data = Fill(beatWords, pstore1_storegen.data) val a_data = Fill(beatWords, pstore1_storegen.data)
val acquire = if (edge.manager.anySupportAcquire) { val acquire = if (edge.manager.anySupportAcquire) {
edge.Acquire(a_source, acquire_address, lgCacheBlockBytes, s2_grow_param)._2 // Cacheability checked by tlb edge.Acquire(a_source, acquire_address, lgCacheBlockBytes, s2_grow_param)._2 // Cacheability checked by tlb