From 1e0aca7358057127f6fa4029d8203a10bbac3bc6 Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Fri, 25 Nov 2016 15:26:22 -0800 Subject: [PATCH] dcache: the high bit of s2_req.typ is the SIGN bit (not size) (#455) --- src/main/scala/rocket/Dcache.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/rocket/Dcache.scala b/src/main/scala/rocket/Dcache.scala index 8b999b0d..635191df 100644 --- a/src/main/scala/rocket/Dcache.scala +++ b/src/main/scala/rocket/Dcache.scala @@ -251,7 +251,7 @@ class DCacheModule(outer: DCache)(implicit p: Parameters) extends HellaCacheModu val a_source = PriorityEncoder(~uncachedInFlight.asUInt) val acquire_address = s2_req_block_addr val access_address = s2_req.addr - val a_size = s2_req.typ + val a_size = s2_req.typ(MT_SZ-2, 0) val a_data = Fill(beatWords, pstore1_storegen.data) val acquire = if (edge.manager.anySupportAcquire) { edge.Acquire(a_source, acquire_address, lgCacheBlockBytes, s2_grow_param)._2 // Cacheability checked by tlb