riscv/rocket-chip
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move htif to uncore

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This commit is contained in:
Yunsup Lee
2013-11-07 13:19:19 -08:00
parent ad1d8f219e
commit 1d6d4b4e96
4 changed files with 4 additions and 4 deletions
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2
rocket

Submodule rocket updated: b1012b2510...f015a75dd3

2
src/main/scala/RocketChip.scala
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@ -157,7 +157,7 @@ class Uncore(htif_width: Int, tileList: Seq[ClientCoherenceAgent])(implicit conf
val mem_backup = new ioMemSerialized(htif_width) val mem_backup = new ioMemSerialized(htif_width)
val mem_backup_en = Bool(INPUT) val mem_backup_en = Bool(INPUT)
} }
val htif = Module(new RocketHTIF(htif_width, conf.nSCR)) val htif = Module(new HTIF(htif_width, PCR.RESET, conf.nSCR))
val outmemsys = Module(new OuterMemorySystem(htif_width, tileList :+ htif)) val outmemsys = Module(new OuterMemorySystem(htif_width, tileList :+ htif))
val incoherentWithHtif = (io.incoherent :+ Bool(true).asInput) val incoherentWithHtif = (io.incoherent :+ Bool(true).asInput)
outmemsys.io.incoherent := incoherentWithHtif outmemsys.io.incoherent := incoherentWithHtif

2
src/main/scala/fpga.scala
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@ -45,7 +45,7 @@ class FPGAUncore(htif_width: Int, tileList: Seq[ClientCoherenceAgent])(implicit
val htif = Vec.fill(conf.nTiles){new HTIFIO(conf.nTiles)}.flip val htif = Vec.fill(conf.nTiles){new HTIFIO(conf.nTiles)}.flip
val incoherent = Vec.fill(conf.nTiles){Bool()}.asInput val incoherent = Vec.fill(conf.nTiles){Bool()}.asInput
} }
val htif = Module(new RocketHTIF(htif_width, conf.nSCR)) val htif = Module(new HTIF(htif_width, PCR.RESET, conf.nSCR))
val outmemsys = Module(new FPGAOuterMemorySystem(htif_width, tileList :+ htif)) val outmemsys = Module(new FPGAOuterMemorySystem(htif_width, tileList :+ htif))
val incoherentWithHtif = (io.incoherent :+ Bool(true).asInput) val incoherentWithHtif = (io.incoherent :+ Bool(true).asInput)
outmemsys.io.incoherent := incoherentWithHtif outmemsys.io.incoherent := incoherentWithHtif

2
uncore

Submodule uncore updated: c0d3194ff8...df449873be