riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

remove top-level Makefile

Browse Source 
new, simpler build instructions are in the README.
note that for "make run-asm-tests-debug" you need to update your fesvr.
This commit is contained in:
Andrew Waterman 2012-02-14 02:53:43 -08:00
parent 15dc2d8c40
commit 1d604bcd49
1 changed files with 2 additions and 16 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

18
rocket/src/main/scala/top.scala
View File

@ -1,4 +1,4 @@
package Top { package Top
import Chisel._ import Chisel._
import Node._; import Node._;
@ -36,20 +36,6 @@ class Top() extends Component {
object top_main { object top_main {
def main(args: Array[String]) = { def main(args: Array[String]) = {
// Can turn off --debug and --vcd when done with debugging to improve emulator performance chiselMain(args, () => new Top());
// val cpu_args = args ++ Array("--target-dir", "generated-src","--debug","--vcd");
// val cpu_args = args ++ Array("--target-dir", "generated-src", "--debug");
val cpu_args = args ++ Array("--target-dir", "generated-src");
// Set variables based off of command flags
// for(a <- args) {
// a match {
// case "-bp" => isBranchPrediction = true;
// case any =>
// }
// }
chiselMain(cpu_args, () => new Top());
} }
} }
}