riscv/rocket-chip
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fix fpga build

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This commit is contained in:
Andrew Waterman 2012-01-13 20:04:11 -08:00
parent addfe55735
commit 1c8f496811
2 changed files with 18 additions and 5 deletions
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5
rocket/src/main/scala/ctrl.scala
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@ -589,8 +589,6 @@ class rocketCtrl extends Component
io.dpath.wen_btb := !ex_btb_match && br_jr_taken && !kill_ex; io.dpath.wen_btb := !ex_btb_match && br_jr_taken && !kill_ex;
io.dpath.stallf := io.dpath.stalld;
// stall for RAW/WAW hazards on loads, AMOs, and mul/div in execute stage. // stall for RAW/WAW hazards on loads, AMOs, and mul/div in execute stage.
val ex_mem_cmd_load = val ex_mem_cmd_load =
ex_reg_mem_val && ((ex_reg_mem_cmd === M_XRD) || ex_reg_mem_cmd(3).toBool); ex_reg_mem_val && ((ex_reg_mem_cmd === M_XRD) || ex_reg_mem_cmd(3).toBool);
@ -649,12 +647,15 @@ class rocketCtrl extends Component
io.dpath.mul_result_val || io.dpath.mul_result_val ||
mem_wb mem_wb
); );
val ctrl_stallf = ctrl_stalld;
val ctrl_killd = take_pc || ctrl_stalld; val ctrl_killd = take_pc || ctrl_stalld;
val ctrl_killf = take_pc || !io.imem.resp_val; val ctrl_killf = take_pc || !io.imem.resp_val;
io.flush_inst := mem_reg_flush_inst; io.flush_inst := mem_reg_flush_inst;
io.dpath.stallf := ctrl_stallf;
io.dpath.stalld := ctrl_stalld; io.dpath.stalld := ctrl_stalld;
io.dpath.killf := ctrl_killf; io.dpath.killf := ctrl_killf;
io.dpath.killd := ctrl_killd; io.dpath.killd := ctrl_killd;

18
rocket/src/main/scala/dpath_util.scala
View File

@ -224,9 +224,21 @@ class ioRegfile extends Bundle()
class rocketDpathRegfile extends Component class rocketDpathRegfile extends Component
{ {
override val io = new ioRegfile(); override val io = new ioRegfile();
val regfile = Mem(32, io.w0.en && (io.w0.addr != UFix(0,5)), io.w0.addr, io.w0.data);
io.r0.data := Mux((io.r0.addr === UFix(0, 5)) || !io.r0.en, Bits(0, 64), regfile(io.r0.addr)); // FIXME: remove the first "if" case once Mem4 C backend bug is fixed
io.r1.data := Mux((io.r1.addr === UFix(0, 5)) || !io.r1.en, Bits(0, 64), regfile(io.r1.addr)); if (SRAM_READ_LATENCY == 0) {
val regfile = Mem(32, io.w0.en && (io.w0.addr != UFix(0,5)), io.w0.addr, io.w0.data);
io.r0.data := Mux((io.r0.addr === UFix(0, 5)) || !io.r0.en, Bits(0, 64), regfile(io.r0.addr));
io.r1.data := Mux((io.r1.addr === UFix(0, 5)) || !io.r1.en, Bits(0, 64), regfile(io.r1.addr));
}
else {
val regfile = Mem4(32, io.w0.data);
regfile.setReadLatency(0);
regfile.setTarget('inst);
regfile.write(io.w0.addr, io.w0.data, io.w0.en);
io.r0.data := Mux((io.r0.addr === UFix(0, 5)) || !io.r0.en, Bits(0, 64), regfile(io.r0.addr));
io.r1.data := Mux((io.r1.addr === UFix(0, 5)) || !io.r1.en, Bits(0, 64), regfile(io.r1.addr));
}
} }
} }