From 1c8f49681185f8db36cb0b8160c4116c90a8e527 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Fri, 13 Jan 2012 20:04:11 -0800 Subject: [PATCH] fix fpga build --- rocket/src/main/scala/ctrl.scala | 5 +++-- rocket/src/main/scala/dpath_util.scala | 18 +++++++++++++++--- 2 files changed, 18 insertions(+), 5 deletions(-) diff --git a/rocket/src/main/scala/ctrl.scala b/rocket/src/main/scala/ctrl.scala index d544c9d1..7d9ba6d9 100644 --- a/rocket/src/main/scala/ctrl.scala +++ b/rocket/src/main/scala/ctrl.scala @@ -589,8 +589,6 @@ class rocketCtrl extends Component io.dpath.wen_btb := !ex_btb_match && br_jr_taken && !kill_ex; - io.dpath.stallf := io.dpath.stalld; - // stall for RAW/WAW hazards on loads, AMOs, and mul/div in execute stage. val ex_mem_cmd_load = ex_reg_mem_val && ((ex_reg_mem_cmd === M_XRD) || ex_reg_mem_cmd(3).toBool); @@ -649,12 +647,15 @@ class rocketCtrl extends Component io.dpath.mul_result_val || mem_wb ); + val ctrl_stallf = ctrl_stalld; val ctrl_killd = take_pc || ctrl_stalld; val ctrl_killf = take_pc || !io.imem.resp_val; io.flush_inst := mem_reg_flush_inst; + + io.dpath.stallf := ctrl_stallf; io.dpath.stalld := ctrl_stalld; io.dpath.killf := ctrl_killf; io.dpath.killd := ctrl_killd; diff --git a/rocket/src/main/scala/dpath_util.scala b/rocket/src/main/scala/dpath_util.scala index 1dd0f3b0..bf13d0c0 100644 --- a/rocket/src/main/scala/dpath_util.scala +++ b/rocket/src/main/scala/dpath_util.scala @@ -224,9 +224,21 @@ class ioRegfile extends Bundle() class rocketDpathRegfile extends Component { override val io = new ioRegfile(); - val regfile = Mem(32, io.w0.en && (io.w0.addr != UFix(0,5)), io.w0.addr, io.w0.data); - io.r0.data := Mux((io.r0.addr === UFix(0, 5)) || !io.r0.en, Bits(0, 64), regfile(io.r0.addr)); - io.r1.data := Mux((io.r1.addr === UFix(0, 5)) || !io.r1.en, Bits(0, 64), regfile(io.r1.addr)); + + // FIXME: remove the first "if" case once Mem4 C backend bug is fixed + if (SRAM_READ_LATENCY == 0) { + val regfile = Mem(32, io.w0.en && (io.w0.addr != UFix(0,5)), io.w0.addr, io.w0.data); + io.r0.data := Mux((io.r0.addr === UFix(0, 5)) || !io.r0.en, Bits(0, 64), regfile(io.r0.addr)); + io.r1.data := Mux((io.r1.addr === UFix(0, 5)) || !io.r1.en, Bits(0, 64), regfile(io.r1.addr)); + } + else { + val regfile = Mem4(32, io.w0.data); + regfile.setReadLatency(0); + regfile.setTarget('inst); + regfile.write(io.w0.addr, io.w0.data, io.w0.en); + io.r0.data := Mux((io.r0.addr === UFix(0, 5)) || !io.r0.en, Bits(0, 64), regfile(io.r0.addr)); + io.r1.data := Mux((io.r1.addr === UFix(0, 5)) || !io.r1.en, Bits(0, 64), regfile(io.r1.addr)); + } } }