fix fpga build
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addfe55735
commit
1c8f496811
@ -589,8 +589,6 @@ class rocketCtrl extends Component
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io.dpath.wen_btb := !ex_btb_match && br_jr_taken && !kill_ex;
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io.dpath.wen_btb := !ex_btb_match && br_jr_taken && !kill_ex;
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io.dpath.stallf := io.dpath.stalld;
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// stall for RAW/WAW hazards on loads, AMOs, and mul/div in execute stage.
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// stall for RAW/WAW hazards on loads, AMOs, and mul/div in execute stage.
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val ex_mem_cmd_load =
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val ex_mem_cmd_load =
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ex_reg_mem_val && ((ex_reg_mem_cmd === M_XRD) || ex_reg_mem_cmd(3).toBool);
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ex_reg_mem_val && ((ex_reg_mem_cmd === M_XRD) || ex_reg_mem_cmd(3).toBool);
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@ -649,12 +647,15 @@ class rocketCtrl extends Component
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io.dpath.mul_result_val ||
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io.dpath.mul_result_val ||
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mem_wb
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mem_wb
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);
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);
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val ctrl_stallf = ctrl_stalld;
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val ctrl_killd = take_pc || ctrl_stalld;
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val ctrl_killd = take_pc || ctrl_stalld;
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val ctrl_killf = take_pc || !io.imem.resp_val;
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val ctrl_killf = take_pc || !io.imem.resp_val;
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io.flush_inst := mem_reg_flush_inst;
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io.flush_inst := mem_reg_flush_inst;
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io.dpath.stallf := ctrl_stallf;
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io.dpath.stalld := ctrl_stalld;
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io.dpath.stalld := ctrl_stalld;
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io.dpath.killf := ctrl_killf;
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io.dpath.killf := ctrl_killf;
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io.dpath.killd := ctrl_killd;
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io.dpath.killd := ctrl_killd;
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@ -224,9 +224,21 @@ class ioRegfile extends Bundle()
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class rocketDpathRegfile extends Component
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class rocketDpathRegfile extends Component
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{
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{
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override val io = new ioRegfile();
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override val io = new ioRegfile();
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// FIXME: remove the first "if" case once Mem4 C backend bug is fixed
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if (SRAM_READ_LATENCY == 0) {
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val regfile = Mem(32, io.w0.en && (io.w0.addr != UFix(0,5)), io.w0.addr, io.w0.data);
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val regfile = Mem(32, io.w0.en && (io.w0.addr != UFix(0,5)), io.w0.addr, io.w0.data);
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io.r0.data := Mux((io.r0.addr === UFix(0, 5)) || !io.r0.en, Bits(0, 64), regfile(io.r0.addr));
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io.r0.data := Mux((io.r0.addr === UFix(0, 5)) || !io.r0.en, Bits(0, 64), regfile(io.r0.addr));
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io.r1.data := Mux((io.r1.addr === UFix(0, 5)) || !io.r1.en, Bits(0, 64), regfile(io.r1.addr));
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io.r1.data := Mux((io.r1.addr === UFix(0, 5)) || !io.r1.en, Bits(0, 64), regfile(io.r1.addr));
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}
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}
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else {
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val regfile = Mem4(32, io.w0.data);
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regfile.setReadLatency(0);
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regfile.setTarget('inst);
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regfile.write(io.w0.addr, io.w0.data, io.w0.en);
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io.r0.data := Mux((io.r0.addr === UFix(0, 5)) || !io.r0.en, Bits(0, 64), regfile(io.r0.addr));
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io.r1.data := Mux((io.r1.addr === UFix(0, 5)) || !io.r1.en, Bits(0, 64), regfile(io.r1.addr));
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}
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}
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}
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}
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