riscv/rocket-chip
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fix fpga build

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This commit is contained in:
Andrew Waterman
2012-01-13 20:04:11 -08:00
parent addfe55735
commit 1c8f496811
2 changed files with 18 additions and 5 deletions
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5
rocket/src/main/scala/ctrl.scala
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@ -589,8 +589,6 @@ class rocketCtrl extends Component
io.dpath.wen_btb := !ex_btb_match && br_jr_taken && !kill_ex;
io.dpath.stallf := io.dpath.stalld;
// stall for RAW/WAW hazards on loads, AMOs, and mul/div in execute stage.
val ex_mem_cmd_load =
ex_reg_mem_val && ((ex_reg_mem_cmd === M_XRD) || ex_reg_mem_cmd(3).toBool);
@ -649,12 +647,15 @@ class rocketCtrl extends Component
io.dpath.mul_result_val ||
mem_wb
);
val ctrl_stallf = ctrl_stalld;
val ctrl_killd = take_pc || ctrl_stalld;
val ctrl_killf = take_pc || !io.imem.resp_val;
io.flush_inst := mem_reg_flush_inst;
io.dpath.stallf := ctrl_stallf;
io.dpath.stalld := ctrl_stalld;
io.dpath.killf := ctrl_killf;
io.dpath.killd := ctrl_killd;