riscv/rocket-chip
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Fixed bug regarding case sensitivity regarding ioICache,ioDCache

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This commit is contained in:
Christopher Celio
2012-02-07 14:07:42 -08:00
parent fde8e3b696
commit 1be9d15944
4 changed files with 12 additions and 12 deletions
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8
rocket/src/main/scala/icache.scala
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@ -18,7 +18,7 @@ class ioImem(view: List[String] = null) extends Bundle (view)
}
// interface between I$ and memory (128 bits wide)
class ioIcache(view: List[String] = null) extends Bundle (view)
class ioICache(view: List[String] = null) extends Bundle (view)
{
val req_addr = UFix(PADDR_BITS - OFFSET_BITS, INPUT);
val req_val = Bool(INPUT);
@ -27,10 +27,10 @@ class ioIcache(view: List[String] = null) extends Bundle (view)
val resp_val = Bool(OUTPUT);
}
class ioICache extends Bundle()
class ioRocketICache extends Bundle()
{
val cpu = new ioImem();
val mem = new ioIcache().flip();
val mem = new ioICache().flip();
}
// basic direct mapped instruction cache
@ -38,7 +38,7 @@ class ioICache extends Bundle()
// parameters :
// lines = # cache lines
class rocketICache(sets: Int, assoc: Int) extends Component {
val io = new ioICache();
val io = new ioRocketICache();
val lines = sets * assoc;
val addrbits = PADDR_BITS;