riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

PLIC: To avoid hazard between enable -> claim, enforce concurrency=1

Browse Source
This commit is contained in:
Megan Wachs 2017-04-19 19:44:51 -07:00
parent 3dfd584075
commit 1be13d6b4c
1 changed files with 2 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
src/main/scala/uncore/devices/Plic.scala
View File

@ -75,7 +75,8 @@ class TLPLIC(maxPriorities: Int, address: BigInt = 0xC000000)(implicit p: Parame
address = Seq(AddressSet(address, PLICConsts.size-1)), address = Seq(AddressSet(address, PLICConsts.size-1)),
device = device, device = device,
beatBytes = p(XLen)/8, beatBytes = p(XLen)/8,
undefZero = false) undefZero = false,
concurrency = 1) // Work around the enable -> claim hazard
val intnode = IntNexusNode( val intnode = IntNexusNode(
numSourcePorts = 0 to 1024, numSourcePorts = 0 to 1024,