Give Rocket priority over DTIM TL port
The TL port can easily starve the processor, even at only 20% utilization, because of a bad interaction with the pipeline. Giving the processor static priority is OK in practice, since <50% of instructions are loads and stores in typical workloads. Even if it executes 100% loads and stores, it must eventually encounter an I$ miss, taken branch, or exception, so even malicious code can't permanently starve the TL port.
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@ -105,8 +105,6 @@ class RocketTileModuleImp(outer: RocketTile) extends BaseTileModuleImp(outer)
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val uncorrectable = RegInit(Bool(false))
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val uncorrectable = RegInit(Bool(false))
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val halt_and_catch_fire = outer.rocketParams.hcfOnUncorrectable.option(IO(Bool(OUTPUT)))
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val halt_and_catch_fire = outer.rocketParams.hcfOnUncorrectable.option(IO(Bool(OUTPUT)))
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outer.dtim_adapter.foreach { lm => dcachePorts += lm.module.io.dmem }
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outer.bus_error_unit.foreach { lm =>
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outer.bus_error_unit.foreach { lm =>
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lm.module.io.errors.dcache := outer.dcache.module.io.errors
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lm.module.io.errors.dcache := outer.dcache.module.io.errors
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lm.module.io.errors.icache := outer.frontend.module.io.errors
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lm.module.io.errors.icache := outer.frontend.module.io.errors
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@ -130,6 +128,9 @@ class RocketTileModuleImp(outer: RocketTile) extends BaseTileModuleImp(outer)
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core.io.rocc.busy := roccCore.busy
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core.io.rocc.busy := roccCore.busy
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core.io.rocc.interrupt := roccCore.interrupt
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core.io.rocc.interrupt := roccCore.interrupt
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// Rocket has higher priority to DTIM than other TileLink clients
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outer.dtim_adapter.foreach { lm => dcachePorts += lm.module.io.dmem }
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when(!uncorrectable) { uncorrectable :=
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when(!uncorrectable) { uncorrectable :=
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List(outer.frontend.module.io.errors, outer.dcache.module.io.errors)
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List(outer.frontend.module.io.errors, outer.dcache.module.io.errors)
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.flatMap { e => e.uncorrectable.map(_.valid) }
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.flatMap { e => e.uncorrectable.map(_.valid) }
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