Merge branch 'master' of github.com:ucb-bar/rocket-chip into tl2-irrevocable

src/main/scala/uncore/devices/Prci.scala

@@ -13,21 +13,11 @@ import cde.{Parameters, Field}
 /** Number of tiles */
 case object NTiles extends Field[Int]
 
-class PRCIInterrupts extends Bundle {
-  val meip = Bool()
-  val seip = Bool()
-  val debug = Bool()
-}
-
 class PRCITileIO(implicit p: Parameters) extends Bundle {
   val reset = Bool(OUTPUT)
-  val id = UInt(OUTPUT, log2Up(p(NTiles)))
-  val interrupts = {
-    val result = new PRCIInterrupts {
-      val mtip = Bool()
-      val msip = Bool()
-    }
-    result.asOutput
+  val interrupts = new Bundle {
+    val mtip = Bool()
+    val msip = Bool()
   }
 
   override def cloneType: this.type = new PRCITileIO().asInstanceOf[this.type]
@@ -47,7 +37,6 @@ class PRCI(implicit val p: Parameters) extends Module
     with HasTileLinkParameters
     with HasAddrMapParameters {
   val io = new Bundle {
-    val interrupts = Vec(p(NTiles), new PRCIInterrupts).asInput
     val tl = new ClientUncachedTileLinkIO().flip
     val tiles = Vec(p(NTiles), new PRCITileIO)
     val rtcTick = Bool(INPUT)
@@ -84,10 +73,9 @@ class PRCI(implicit val p: Parameters) extends Module
   }
 
   for ((tile, i) <- io.tiles zipWithIndex) {
-    tile.interrupts := io.interrupts(i)
     tile.interrupts.msip := ipi(i)(0)
     tile.interrupts.mtip := time >= timecmp(i)
-    tile.id := UInt(i)
+    tile.reset := reset
   }
 
   // TODO generalize these to help other TL slaves

src/main/scala/uncore/tilelink2/RegisterCrossing.scala

@@ -5,6 +5,7 @@ package uncore.tilelink2
 import Chisel._
 import chisel3.util.{Irrevocable, IrrevocableIO}
 import junctions._
+import uncore.util.{AsyncResetRegVec}
 
 // A very simple flow control state machine, run in the specified clock domain
 class BusyRegisterCrossing(clock: Clock, reset: Bool)
@@ -131,3 +132,56 @@ class RegisterReadCrossing[T <: Data](gen: T, sync: Int = 3) extends Module {
   crossing.io.deq.ready := io.master_port.request.valid && !reg.io.busy
   crossing.io.enq.valid := Bool(true)
 }
+
+/** Wrapper to create an
+  *  asynchronously reset
+  *  slave register which
+  *  can be both read
+  *  and written using
+  *  crossing FIFOs.
+  */
+
+object AsyncRWSlaveRegField {
+
+  def apply(slave_clock: Clock,
+    slave_reset: Bool,
+    width:  Int,
+    init: Int,
+    master_allow: Bool = Bool(true),
+    slave_allow: Bool = Bool(true)
+  ): (UInt, RegField) = {
+
+    val async_slave_reg = Module(new AsyncResetRegVec(width, init))
+    async_slave_reg.reset := slave_reset
+    async_slave_reg.clock := slave_clock
+
+    val wr_crossing = Module (new RegisterWriteCrossing(UInt(width = width)))
+
+    val scope = Module (new AsyncScope())
+
+    wr_crossing.io.master_clock := scope.clock
+    wr_crossing.io.master_reset := scope.reset
+    wr_crossing.io.master_allow := master_allow
+    wr_crossing.io.slave_clock  := slave_clock
+    wr_crossing.io.slave_reset  := slave_reset
+    wr_crossing.io.slave_allow  := slave_allow
+
+    async_slave_reg.io.en := wr_crossing.io.slave_valid
+    async_slave_reg.io.d  := wr_crossing.io.slave_register
+
+    val rd_crossing = Module (new RegisterReadCrossing(UInt(width = width )))
+
+    rd_crossing.io.master_clock := scope.clock
+    rd_crossing.io.master_reset := scope.reset
+    rd_crossing.io.master_allow := master_allow
+    rd_crossing.io.slave_clock  := slave_clock
+    rd_crossing.io.slave_reset  := slave_reset
+    rd_crossing.io.slave_allow  := slave_allow
+
+    rd_crossing.io.slave_register := async_slave_reg.io.q
+
+    (async_slave_reg.io.q, RegField(width, rd_crossing.io.master_port, wr_crossing.io.master_port))
+
+  }
+
+}