Merge branch 'master' of github.com:ucb-bar/rocket-chip into tl2-irrevocable

src/main/scala/junctions/crossing.scala

@@ -83,5 +83,44 @@ object AsyncIrrevocableFrom
   // takes from_source from the 'from' clock domain and puts it into your clock domain
   def apply[T <: Data](from_clock: Clock, from_reset: Bool, from_source: ReadyValidIO[T], depth: Int = 8, sync: Int = 3): IrrevocableIO[T] = {
     PostQueueIrrevocablize(AsyncDecoupledFrom(from_clock, from_reset, from_source, depth, sync))
+}
+
+/**  Because Chisel/FIRRTL does not allow us
+  *  to directly assign clocks from Signals,
+  *  we need this black box module.
+  *  This may even be useful because some back-end
+  *  flows like to have this sort of transition
+  *  flagged with a special cell or module anyway.
+  */
+
+class SignalToClock extends BlackBox {
+  val io = new Bundle {
+    val signal_in = Bool(INPUT)
+    val clock_out = Clock(OUTPUT)
+  }
+
+  //  io.clock_out := io.signal_in
+}
+
+object SignalToClock {
+  def apply(signal: Bool): Clock = {
+    val s2c = Module(new SignalToClock)
+    s2c.io.signal_in := signal
+    s2c.io.clock_out
+  }
+}
+
+class ClockToSignal extends BlackBox {
+  val io = new Bundle {
+    val clock_in = Clock(INPUT)
+    val signal_out = Bool(OUTPUT)
+  }
+}
+
+object ClockToSignal {
+  def apply(clk: Clock): Bool = {
+    val c2s = Module(new ClockToSignal)
+    c2s.io.clock_in := clk
+    c2s.io.signal_out
   }
 }

src/main/scala/junctions/hasti.scala

@@ -521,10 +521,8 @@ class HastiTestSRAM(depth: Int)(implicit p: Parameters) extends HastiModule()(p)
   // In case we are stalled, we need to hold the read data
   val d_rdata = holdUnless(mem.read(a_address, read), RegNext(read))
   // Whenever the port is not needed for reading, execute pending writes
-  when (!read) {
-    when (p_valid) { mem.write(p_address, p_wdata, p_mask.toBools) }
-    p_valid := Bool(false)
-  }
+  when (!read && p_valid) { mem.write(p_address, p_wdata, p_mask.toBools) }
+  when (!read) { p_valid := Bool(false) }
   
   // Record the request for later?
   when (ready && a_request && a_write) {