riscv/rocket-chip
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simplify base Coreplex bundle

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This commit is contained in:
Yunsup Lee 2016-09-21 18:27:31 -07:00
parent d2df6397cd
commit 1b1ef3be07
2 changed files with 9 additions and 11 deletions
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15
src/main/scala/coreplex/BaseCoreplex.scala
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@ -41,8 +41,7 @@ case class CoreplexConfig(
nExtInterrupts: Int, nExtInterrupts: Int,
nSlaves: Int, nSlaves: Int,
nMemChannels: Int, nMemChannels: Int,
hasSupervisor: Boolean, hasSupervisor: Boolean)
hasExtMMIOPort: Boolean)
{ {
val plicKey = PLICConfig(nTiles, hasSupervisor, nExtInterrupts, 0) val plicKey = PLICConfig(nTiles, hasSupervisor, nExtInterrupts, 0)
} }
@ -52,14 +51,14 @@ abstract class BaseCoreplex(c: CoreplexConfig)(implicit p: Parameters) extends L
abstract class BaseCoreplexBundle(val c: CoreplexConfig)(implicit val p: Parameters) extends Bundle with HasCoreplexParameters { abstract class BaseCoreplexBundle(val c: CoreplexConfig)(implicit val p: Parameters) extends Bundle with HasCoreplexParameters {
val master = new Bundle { val master = new Bundle {
val mem = Vec(c.nMemChannels, new ClientUncachedTileLinkIO()(outermostParams)) val mem = Vec(c.nMemChannels, new ClientUncachedTileLinkIO()(outermostParams))
val mmio = c.hasExtMMIOPort.option(new ClientUncachedTileLinkIO()(outermostMMIOParams)) val mmio = new ClientUncachedTileLinkIO()(outermostMMIOParams)
} }
val slave = Vec(c.nSlaves, new ClientUncachedTileLinkIO()(innerParams)).flip val slave = Vec(c.nSlaves, new ClientUncachedTileLinkIO()(innerParams)).flip
val interrupts = Vec(c.nExtInterrupts, Bool()).asInput val interrupts = Vec(c.nExtInterrupts, Bool()).asInput
val debug = new DebugBusIO()(p).flip val debug = new DebugBusIO()(p).flip
val clint = Vec(c.nTiles, new CoreplexLocalInterrupts).asInput val clint = Vec(c.nTiles, new CoreplexLocalInterrupts).asInput
val success = Bool(OUTPUT)
val resetVector = UInt(INPUT, p(XLen)) val resetVector = UInt(INPUT, p(XLen))
val success = Bool(OUTPUT) // used for testing
} }
abstract class BaseCoreplexModule[+L <: BaseCoreplex, +B <: BaseCoreplexBundle]( abstract class BaseCoreplexModule[+L <: BaseCoreplex, +B <: BaseCoreplexBundle](
@ -67,9 +66,6 @@ abstract class BaseCoreplexModule[+L <: BaseCoreplex, +B <: BaseCoreplexBundle](
val outer: L = l val outer: L = l
val io: B = b val io: B = b
// Coreplex doesn't know when to stop running
io.success := Bool(false)
// Build a set of Tiles // Build a set of Tiles
val tiles = p(BuildTiles) map { _(reset, p) } val tiles = p(BuildTiles) map { _(reset, p) }
val uncoreTileIOs = (tiles zipWithIndex) map { case (tile, i) => Wire(tile.io) } val uncoreTileIOs = (tiles zipWithIndex) map { case (tile, i) => Wire(tile.io) }
@ -162,6 +158,9 @@ abstract class BaseCoreplexModule[+L <: BaseCoreplex, +B <: BaseCoreplexBundle](
for ((t, m) <- (uncoreTileIOs.map(_.slave).flatten) zip (tileSlavePorts map (cBus port _))) for ((t, m) <- (uncoreTileIOs.map(_.slave).flatten) zip (tileSlavePorts map (cBus port _)))
t <> m t <> m
io.master.mmio.foreach { _ <> cBus.port("pbus") } io.master.mmio <> cBus.port("pbus")
} }
// Coreplex doesn't know when to stop running
io.success := Bool(false)
} }

5
src/main/scala/rocketchip/BaseTop.scala
View File

@ -36,8 +36,7 @@ abstract class BaseTop(q: Parameters) extends LazyModule {
nExtInterrupts = pInterrupts.sum, nExtInterrupts = pInterrupts.sum,
nSlaves = pBusMasters.sum, nSlaves = pBusMasters.sum,
nMemChannels = q(NMemoryChannels), nMemChannels = q(NMemoryChannels),
hasSupervisor = q(UseVM), hasSupervisor = q(UseVM)
hasExtMMIOPort = true
) )
lazy val genGlobalAddrMap = GenerateGlobalAddrMap(q, pDevices.get, peripheryManagers) lazy val genGlobalAddrMap = GenerateGlobalAddrMap(q, pDevices.get, peripheryManagers)
@ -68,7 +67,7 @@ abstract class BaseTopModule[+L <: BaseTop, +B <: BaseTopBundle](
val pBus = val pBus =
Module(new TileLinkRecursiveInterconnect(1, p(GlobalAddrMap).subMap("io:pbus"))( Module(new TileLinkRecursiveInterconnect(1, p(GlobalAddrMap).subMap("io:pbus"))(
p.alterPartial({ case TLId => "L2toMMIO" }))) p.alterPartial({ case TLId => "L2toMMIO" })))
pBus.io.in.head <> coreplexIO.master.mmio.get pBus.io.in.head <> coreplexIO.master.mmio
outer.legacy.module.io.legacy <> pBus.port("TL2") outer.legacy.module.io.legacy <> pBus.port("TL2")
println("Generated Address Map") println("Generated Address Map")