From 1b1ef3be07d5c1d2341b51a147675e93e9e7346e Mon Sep 17 00:00:00 2001
From: Yunsup Lee <yunsup@sifive.com>
Date: Wed, 21 Sep 2016 18:27:31 -0700
Subject: [PATCH] simplify base Coreplex bundle

---
 src/main/scala/coreplex/BaseCoreplex.scala | 15 +++++++--------
 src/main/scala/rocketchip/BaseTop.scala    |  5 ++---
 2 files changed, 9 insertions(+), 11 deletions(-)

diff --git a/src/main/scala/coreplex/BaseCoreplex.scala b/src/main/scala/coreplex/BaseCoreplex.scala
index c893f930..7c5a25f7 100644
--- a/src/main/scala/coreplex/BaseCoreplex.scala
+++ b/src/main/scala/coreplex/BaseCoreplex.scala
@@ -41,8 +41,7 @@ case class CoreplexConfig(
     nExtInterrupts: Int,
     nSlaves: Int,
     nMemChannels: Int,
-    hasSupervisor: Boolean,
-    hasExtMMIOPort: Boolean)
+    hasSupervisor: Boolean)
 {
   val plicKey = PLICConfig(nTiles, hasSupervisor, nExtInterrupts, 0)
 }
@@ -52,14 +51,14 @@ abstract class BaseCoreplex(c: CoreplexConfig)(implicit p: Parameters) extends L
 abstract class BaseCoreplexBundle(val c: CoreplexConfig)(implicit val p: Parameters) extends Bundle with HasCoreplexParameters {
   val master = new Bundle {
     val mem = Vec(c.nMemChannels, new ClientUncachedTileLinkIO()(outermostParams))
-    val mmio = c.hasExtMMIOPort.option(new ClientUncachedTileLinkIO()(outermostMMIOParams))
+    val mmio = new ClientUncachedTileLinkIO()(outermostMMIOParams)
   }
   val slave = Vec(c.nSlaves, new ClientUncachedTileLinkIO()(innerParams)).flip
   val interrupts = Vec(c.nExtInterrupts, Bool()).asInput
   val debug = new DebugBusIO()(p).flip
   val clint = Vec(c.nTiles, new CoreplexLocalInterrupts).asInput
-  val success = Bool(OUTPUT)
   val resetVector = UInt(INPUT, p(XLen))
+  val success = Bool(OUTPUT) // used for testing
 }
 
 abstract class BaseCoreplexModule[+L <: BaseCoreplex, +B <: BaseCoreplexBundle](
@@ -67,9 +66,6 @@ abstract class BaseCoreplexModule[+L <: BaseCoreplex, +B <: BaseCoreplexBundle](
   val outer: L = l
   val io: B = b
 
-  // Coreplex doesn't know when to stop running
-  io.success := Bool(false)
-
   // Build a set of Tiles
   val tiles = p(BuildTiles) map { _(reset, p) }
   val uncoreTileIOs = (tiles zipWithIndex) map { case (tile, i) => Wire(tile.io) }
@@ -162,6 +158,9 @@ abstract class BaseCoreplexModule[+L <: BaseCoreplex, +B <: BaseCoreplexBundle](
     for ((t, m) <- (uncoreTileIOs.map(_.slave).flatten) zip (tileSlavePorts map (cBus port _)))
       t <> m
 
-    io.master.mmio.foreach { _ <> cBus.port("pbus") }
+    io.master.mmio <> cBus.port("pbus")
   }
+
+  // Coreplex doesn't know when to stop running
+  io.success := Bool(false)
 }
diff --git a/src/main/scala/rocketchip/BaseTop.scala b/src/main/scala/rocketchip/BaseTop.scala
index ea0777e5..74892489 100644
--- a/src/main/scala/rocketchip/BaseTop.scala
+++ b/src/main/scala/rocketchip/BaseTop.scala
@@ -36,8 +36,7 @@ abstract class BaseTop(q: Parameters) extends LazyModule {
     nExtInterrupts = pInterrupts.sum,
     nSlaves = pBusMasters.sum,
     nMemChannels = q(NMemoryChannels),
-    hasSupervisor = q(UseVM),
-    hasExtMMIOPort = true
+    hasSupervisor = q(UseVM)
   )
 
   lazy val genGlobalAddrMap = GenerateGlobalAddrMap(q, pDevices.get, peripheryManagers)
@@ -68,7 +67,7 @@ abstract class BaseTopModule[+L <: BaseTop, +B <: BaseTopBundle](
   val pBus =
     Module(new TileLinkRecursiveInterconnect(1, p(GlobalAddrMap).subMap("io:pbus"))(
       p.alterPartial({ case TLId => "L2toMMIO" })))
-  pBus.io.in.head <> coreplexIO.master.mmio.get
+  pBus.io.in.head <> coreplexIO.master.mmio
   outer.legacy.module.io.legacy <> pBus.port("TL2")
 
   println("Generated Address Map")