riscv/rocket-chip
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simplify base Coreplex bundle

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Yunsup Lee
2016-09-21 18:27:31 -07:00
parent d2df6397cd
commit 1b1ef3be07
2 changed files with 9 additions and 11 deletions
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5
src/main/scala/rocketchip/BaseTop.scala
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@@ -36,8 +36,7 @@ abstract class BaseTop(q: Parameters) extends LazyModule {
nExtInterrupts = pInterrupts.sum,
nSlaves = pBusMasters.sum,
nMemChannels = q(NMemoryChannels),
hasSupervisor = q(UseVM),
hasExtMMIOPort = true
hasSupervisor = q(UseVM)
)
lazy val genGlobalAddrMap = GenerateGlobalAddrMap(q, pDevices.get, peripheryManagers)
@@ -68,7 +67,7 @@ abstract class BaseTopModule[+L <: BaseTop, +B <: BaseTopBundle](
val pBus =
Module(new TileLinkRecursiveInterconnect(1, p(GlobalAddrMap).subMap("io:pbus"))(
p.alterPartial({ case TLId => "L2toMMIO" })))
pBus.io.in.head <> coreplexIO.master.mmio.get
pBus.io.in.head <> coreplexIO.master.mmio
outer.legacy.module.io.legacy <> pBus.port("TL2")
println("Generated Address Map")