riscv/rocket-chip
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TLSplitter: QoR improvements

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Track commit 985d9750e6
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Wesley W. Terpstra
2017-06-20 14:01:07 -07:00
parent f6e0dd12c8
commit 1aa4f5ce33
1 changed files with 1 additions and 1 deletions
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src/main/scala/uncore/tilelink2/Splitter.scala
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@@ -51,7 +51,7 @@ class TLSplitter(policy: TLArbiter.Policy = TLArbiter.lowestIndexFirst)(implicit
// Find a good mask for address decoding // Find a good mask for address decoding
val port_addrs = edgesOut.map(_.manager.managers.map(_.address).flatten) val port_addrs = edgesOut.map(_.manager.managers.map(_.address).flatten)
val routingMask = AddressDecoder(port_addrs) val routingMask = AddressDecoder(port_addrs)
val route_addrs = port_addrs.map(_.map(_.widen(~routingMask)).distinct) val route_addrs = port_addrs.map(seq => AddressSet.unify(seq.map(_.widen(~routingMask)).distinct))
val outputPorts = route_addrs.map(seq => (addr: UInt) => seq.map(_.contains(addr)).reduce(_ || _)) val outputPorts = route_addrs.map(seq => (addr: UInt) => seq.map(_.contains(addr)).reduce(_ || _))
// We need an intermediate size of bundle with the widest possible identifiers // We need an intermediate size of bundle with the widest possible identifiers