riscv/rocket-chip
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coreplex: add externalSlaveBuffers configuration option

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This commit is contained in:
Wesley W. Terpstra 2017-09-06 14:58:34 -07:00
parent fd8a51a910
commit 1a87ed1193
2 changed files with 5 additions and 4 deletions
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6
src/main/scala/coreplex/RocketCoreplex.scala
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@ -46,19 +46,19 @@ trait HasRocketTiles extends HasSystemBus
case SynchronousCrossing(params) => {
val wrapper = LazyModule(new SyncRocketTile(tp, i)(pWithExtra))
sbus.fromSyncTiles(params, tp.externalMasterBuffers, tp.name) :=* wrapper.masterNode
wrapper.slaveNode :*= pbus.bufferToSlaves
wrapper.slaveNode :*= pbus.toSyncSlaves(tp.name, tp.externalSlaveBuffers)
wrapper
}
case AsynchronousCrossing(depth, sync) => {
val wrapper = LazyModule(new AsyncRocketTile(tp, i)(pWithExtra))
sbus.fromAsyncTiles(depth, sync, tp.externalMasterBuffers, tp.name) :=* wrapper.masterNode
wrapper.slaveNode :*= pbus.toAsyncSlaves(sync, tp.name)
wrapper.slaveNode :*= pbus.toAsyncSlaves(sync, tp.name, tp.externalSlaveBuffers)
wrapper
}
case RationalCrossing(direction) => {
val wrapper = LazyModule(new RationalRocketTile(tp, i)(pWithExtra))
sbus.fromRationalTiles(direction, tp.externalMasterBuffers, tp.name) :=* wrapper.masterNode
wrapper.slaveNode :*= pbus.toRationalSlaves(tp.name)
wrapper.slaveNode :*= pbus.toRationalSlaves(tp.name, tp.externalSlaveBuffers)
wrapper
}
}

3
src/main/scala/tile/RocketTile.scala
View File

@ -20,7 +20,8 @@ case class RocketTileParams(
dataScratchpadBytes: Int = 0,
boundaryBuffers: Boolean = false,
name: Option[String] = Some("tile"),
externalMasterBuffers: Int = 0) extends TileParams {
externalMasterBuffers: Int = 0,
externalSlaveBuffers: Int = 0) extends TileParams {
require(icache.isDefined)
require(dcache.isDefined)
}