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apb: SRAM reports errors on illegal access

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This commit is contained in:
Wesley W. Terpstra 2017-07-07 19:38:45 -07:00
parent 025f7d890b
commit 19851a7c9e
1 changed files with 3 additions and 2 deletions
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src/main/scala/amba/apb/SRAM.scala
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@ -32,17 +32,18 @@ class APBRAM(address: AddressSet, executable: Boolean = true, beatBytes: Int = 4
if (x == 0) tail.reverse else bigBits(x >> 1, ((x & 1) == 1) :: tail) if (x == 0) tail.reverse else bigBits(x >> 1, ((x & 1) == 1) :: tail)
val mask = bigBits(address.mask >> log2Ceil(beatBytes)) val mask = bigBits(address.mask >> log2Ceil(beatBytes))
val paddr = Cat((mask zip (in.paddr >> log2Ceil(beatBytes)).toBools).filter(_._1).map(_._2).reverse) val paddr = Cat((mask zip (in.paddr >> log2Ceil(beatBytes)).toBools).filter(_._1).map(_._2).reverse)
val legal = address.contains(in.paddr)
// Use single-ported memory with byte-write enable // Use single-ported memory with byte-write enable
val mem = SeqMem(1 << mask.filter(b=>b).size, Vec(beatBytes, Bits(width = 8))) val mem = SeqMem(1 << mask.filter(b=>b).size, Vec(beatBytes, Bits(width = 8)))
val read = in.psel && !in.penable && !in.pwrite val read = in.psel && !in.penable && !in.pwrite
when (in.psel && !in.penable && in.pwrite) { when (in.psel && !in.penable && in.pwrite && legal) {
mem.write(paddr, Vec.tabulate(beatBytes) { i => in.pwdata(8*(i+1)-1, 8*i) }, in.pstrb.toBools) mem.write(paddr, Vec.tabulate(beatBytes) { i => in.pwdata(8*(i+1)-1, 8*i) }, in.pstrb.toBools)
} }
in.pready := Bool(true) in.pready := Bool(true)
in.pslverr := Bool(false) in.pslverr := RegNext(!legal)
in.prdata := mem.readAndHold(paddr, read).asUInt in.prdata := mem.readAndHold(paddr, read).asUInt
} }
} }