From 19851a7c9eaf9f06cbfbe0232730448465402040 Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Fri, 7 Jul 2017 19:38:45 -0700 Subject: [PATCH] apb: SRAM reports errors on illegal access --- src/main/scala/amba/apb/SRAM.scala | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/main/scala/amba/apb/SRAM.scala b/src/main/scala/amba/apb/SRAM.scala index 57babb9c..e74fb9a2 100644 --- a/src/main/scala/amba/apb/SRAM.scala +++ b/src/main/scala/amba/apb/SRAM.scala @@ -32,17 +32,18 @@ class APBRAM(address: AddressSet, executable: Boolean = true, beatBytes: Int = 4 if (x == 0) tail.reverse else bigBits(x >> 1, ((x & 1) == 1) :: tail) val mask = bigBits(address.mask >> log2Ceil(beatBytes)) val paddr = Cat((mask zip (in.paddr >> log2Ceil(beatBytes)).toBools).filter(_._1).map(_._2).reverse) + val legal = address.contains(in.paddr) // Use single-ported memory with byte-write enable val mem = SeqMem(1 << mask.filter(b=>b).size, Vec(beatBytes, Bits(width = 8))) val read = in.psel && !in.penable && !in.pwrite - when (in.psel && !in.penable && in.pwrite) { + when (in.psel && !in.penable && in.pwrite && legal) { mem.write(paddr, Vec.tabulate(beatBytes) { i => in.pwdata(8*(i+1)-1, 8*i) }, in.pstrb.toBools) } in.pready := Bool(true) - in.pslverr := Bool(false) + in.pslverr := RegNext(!legal) in.prdata := mem.readAndHold(paddr, read).asUInt } }