riscv/rocket-chip
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add id field to NastiWriteDataChannel

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This commit is contained in:
Howard Mao 2016-04-19 09:38:04 -07:00
parent 42c4d1e51f
commit 1967186a96
2 changed files with 22 additions and 16 deletions
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30
junctions/src/main/scala/atos.scala
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@ -8,7 +8,8 @@ trait HasAtosParameters extends HasNastiParameters {
// round up to a multiple of 32 // round up to a multiple of 32
def roundup(n: Int) = 32 * ((n - 1) / 32 + 1) def roundup(n: Int) = 32 * ((n - 1) / 32 + 1)
val atosUnionBits = max(nastiXDataBits + nastiWStrobeBits + 1, val atosUnionBits = max(
nastiXIdBits + nastiXDataBits + nastiWStrobeBits + 1,
nastiXIdBits + nastiXBurstBits + nastiXIdBits + nastiXBurstBits +
nastiXSizeBits + nastiXLenBits + nastiXAddrBits) nastiXSizeBits + nastiXLenBits + nastiXAddrBits)
val atosIdBits = nastiXIdBits val atosIdBits = nastiXIdBits
@ -16,11 +17,13 @@ trait HasAtosParameters extends HasNastiParameters {
val atosRespBits = nastiXRespBits val atosRespBits = nastiXRespBits
val atosDataBits = nastiXDataBits val atosDataBits = nastiXDataBits
val atosLenOffset = nastiXAddrBits val atosAddrOffset = atosIdBits
val atosLenOffset = atosIdBits + nastiXAddrBits
val atosSizeOffset = atosLenOffset + nastiXLenBits val atosSizeOffset = atosLenOffset + nastiXLenBits
val atosBurstOffset = atosSizeOffset + nastiXSizeBits val atosBurstOffset = atosSizeOffset + nastiXSizeBits
val atosIdOffset = atosBurstOffset + nastiXBurstBits
val atosStrobeOffset = nastiXDataBits val atosDataOffset = atosIdBits
val atosStrobeOffset = nastiXDataBits + atosIdBits
val atosLastOffset = atosStrobeOffset + nastiWStrobeBits val atosLastOffset = atosStrobeOffset + nastiWStrobeBits
val atosRequestBits = roundup(atosTypBits + atosUnionBits) val atosRequestBits = roundup(atosTypBits + atosUnionBits)
@ -49,13 +52,13 @@ object AtosRequest {
} }
def apply(ar: NastiReadAddressChannel)(implicit p: Parameters): AtosRequest = def apply(ar: NastiReadAddressChannel)(implicit p: Parameters): AtosRequest =
apply(arType, Cat(ar.id, ar.burst, ar.size, ar.len, ar.addr)) apply(arType, Cat(ar.burst, ar.size, ar.len, ar.addr, ar.id))
def apply(aw: NastiWriteAddressChannel)(implicit p: Parameters): AtosRequest = def apply(aw: NastiWriteAddressChannel)(implicit p: Parameters): AtosRequest =
apply(awType, Cat(aw.id, aw.burst, aw.size, aw.len, aw.addr)) apply(awType, Cat(aw.burst, aw.size, aw.len, aw.addr, aw.id))
def apply(w: NastiWriteDataChannel)(implicit p: Parameters): AtosRequest = def apply(w: NastiWriteDataChannel)(implicit p: Parameters): AtosRequest =
apply(wType, Cat(w.last, w.strb, w.data)) apply(wType, Cat(w.last, w.strb, w.data, w.id))
} }
class AtosRequest(implicit p: Parameters) class AtosRequest(implicit p: Parameters)
@ -63,11 +66,8 @@ class AtosRequest(implicit p: Parameters)
val typ = UInt(width = atosTypBits) val typ = UInt(width = atosTypBits)
val union = UInt(width = atosUnionBits) val union = UInt(width = atosUnionBits)
def id(dummy: Int = 0) =
union(atosIdOffset + nastiXIdBits - 1, atosIdOffset)
def burst(dummy: Int = 0) = def burst(dummy: Int = 0) =
union(atosIdOffset - 1, atosBurstOffset) union(atosUnionBits - 1, atosBurstOffset)
def size(dummy: Int = 0) = def size(dummy: Int = 0) =
union(atosBurstOffset - 1, atosSizeOffset) union(atosBurstOffset - 1, atosSizeOffset)
@ -76,10 +76,13 @@ class AtosRequest(implicit p: Parameters)
union(atosSizeOffset - 1, atosLenOffset) union(atosSizeOffset - 1, atosLenOffset)
def addr(dummy: Int = 0) = def addr(dummy: Int = 0) =
union(atosLenOffset - 1, 0) union(atosLenOffset - 1, atosAddrOffset)
def id(dummy: Int = 0) =
union(atosIdBits - 1, 0)
def data(dummy: Int = 0) = def data(dummy: Int = 0) =
union(nastiXDataBits - 1, 0) union(atosStrobeOffset - 1, atosDataOffset)
def strb(dummy: Int = 0) = def strb(dummy: Int = 0) =
union(atosLastOffset - 1, atosStrobeOffset) union(atosLastOffset - 1, atosStrobeOffset)
@ -241,6 +244,7 @@ class AtosRequestDecoder(implicit p: Parameters) extends AtosModule()(p) {
io.w.valid := io.req.valid && is_w io.w.valid := io.req.valid && is_w
io.w.bits := NastiWriteDataChannel( io.w.bits := NastiWriteDataChannel(
id = io.req.bits.id(),
data = io.req.bits.data(), data = io.req.bits.data(),
strb = io.req.bits.strb(), strb = io.req.bits.strb(),
last = io.req.bits.last()) last = io.req.bits.last())

8
junctions/src/main/scala/nasti.scala
View File

@ -93,6 +93,7 @@ class NastiWriteAddressChannel(implicit p: Parameters) extends NastiAddressChann
class NastiWriteDataChannel(implicit p: Parameters) extends NastiMasterToSlaveChannel()(p) class NastiWriteDataChannel(implicit p: Parameters) extends NastiMasterToSlaveChannel()(p)
with HasNastiData { with HasNastiData {
val id = UInt(width = nastiWIdBits)
val strb = UInt(width = nastiWStrobeBits) val strb = UInt(width = nastiWStrobeBits)
val user = UInt(width = nastiWUserBits) val user = UInt(width = nastiWUserBits)
} }
@ -167,7 +168,8 @@ object NastiReadAddressChannel {
} }
object NastiWriteDataChannel { object NastiWriteDataChannel {
def apply(data: UInt, last: Bool = Bool(true))(implicit p: Parameters): NastiWriteDataChannel = { def apply(data: UInt, last: Bool = Bool(true), id: UInt = UInt(0))
(implicit p: Parameters): NastiWriteDataChannel = {
val w = Wire(new NastiWriteDataChannel) val w = Wire(new NastiWriteDataChannel)
w.strb := Fill(w.nastiWStrobeBits, UInt(1, 1)) w.strb := Fill(w.nastiWStrobeBits, UInt(1, 1))
w.data := data w.data := data
@ -175,9 +177,9 @@ object NastiWriteDataChannel {
w.user := UInt(0) w.user := UInt(0)
w w
} }
def apply(data: UInt, strb: UInt, last: Bool) def apply(data: UInt, strb: UInt, last: Bool, id: UInt)
(implicit p: Parameters): NastiWriteDataChannel = { (implicit p: Parameters): NastiWriteDataChannel = {
val w = apply(data, last) val w = apply(data, last, id)
w.strb := strb w.strb := strb
w w
} }