riscv/rocket-chip
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make sure to generate release from clean coh state on probe miss

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This commit is contained in:
Howard Mao 2015-09-30 16:58:10 -07:00
parent 833909a2b5
commit 19656e4abe
1 changed files with 3 additions and 1 deletions
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4
rocket/src/main/scala/nbdcache.scala
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@ -630,7 +630,9 @@ class ProbeUnit extends L1HellaCacheModule {
req := io.req.bits req := io.req.bits
} }
val reply = old_coh.makeRelease(req) val miss_coh = ClientMetadata.onReset
val reply_coh = Mux(tag_matches, old_coh, miss_coh)
val reply = reply_coh.makeRelease(req)
io.req.ready := state === s_invalid io.req.ready := state === s_invalid
io.rep.valid := state === s_release && io.rep.valid := state === s_release &&
!(tag_matches && old_coh.requiresVoluntaryWriteback()) // Otherwise WBU will issue release !(tag_matches && old_coh.requiresVoluntaryWriteback()) // Otherwise WBU will issue release