riscv/rocket-chip
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Added coherence message type enums

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This commit is contained in:
Henry Cook 2012-02-22 10:12:13 -08:00
parent 22f8dd0994
commit 18bd0c232b
2 changed files with 15 additions and 4 deletions
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8
rocket/src/main/scala/coherence.scala
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@ -4,7 +4,7 @@ import Chisel._
import Constants._ import Constants._
class TransactionInit extends Bundle { class TransactionInit extends Bundle {
val ttype = Bits(width = 2) val ttype = Bits(width = TTYPE_BITS)
val tileTransactionID = Bits(width = TILE_XACT_ID_BITS) val tileTransactionID = Bits(width = TILE_XACT_ID_BITS)
val address = Bits(width = PADDR_BITS) val address = Bits(width = PADDR_BITS)
val data = Bits(width = MEM_DATA_BITS) val data = Bits(width = MEM_DATA_BITS)
@ -15,20 +15,20 @@ class TransactionAbort extends Bundle {
} }
class ProbeRequest extends Bundle { class ProbeRequest extends Bundle {
val ptype = Bits(width = 2) val ptype = Bits(width = PTYPE_BITS)
val globalTransactionID = Bits(width = GLOBAL_XACT_ID_BITS) val globalTransactionID = Bits(width = GLOBAL_XACT_ID_BITS)
val address = Bits(width = PADDR_BITS) val address = Bits(width = PADDR_BITS)
} }
class ProbeReply extends Bundle { class ProbeReply extends Bundle {
val ptype = Bits(width = 2) val ptype = Bits(width = PTYPE_BITS)
val hasData = Bool() val hasData = Bool()
val globalTransactionID = Bits(width = GLOBAL_XACT_ID_BITS) val globalTransactionID = Bits(width = GLOBAL_XACT_ID_BITS)
val data = Bits(width = MEM_DATA_BITS) val data = Bits(width = MEM_DATA_BITS)
} }
class TransactionReply extends Bundle { class TransactionReply extends Bundle {
val ttype = Bits(width = 2) val ttype = Bits(width = TTYPE_BITS)
val tileTransactionID = Bits(width = TILE_XACT_ID_BITS) val tileTransactionID = Bits(width = TILE_XACT_ID_BITS)
val globalTransactionID = Bits(width = GLOBAL_XACT_ID_BITS) val globalTransactionID = Bits(width = GLOBAL_XACT_ID_BITS)
val data = Bits(width = MEM_DATA_BITS) val data = Bits(width = MEM_DATA_BITS)

11
rocket/src/main/scala/consts.scala
View File

@ -177,6 +177,17 @@ object Constants
val TILE_XACT_ID_BITS = 1; // log2(NMSHR) val TILE_XACT_ID_BITS = 1; // log2(NMSHR)
val GLOBAL_XACT_ID_BITS = IDX_BITS; // if one active xact per set val GLOBAL_XACT_ID_BITS = IDX_BITS; // if one active xact per set
val TTYPE_BITS = 2
val X_READ_SHARED = UFix(0, TTYPE_BITS)
val X_READ_EXCLUSIVE = UFix(1, TTYPE_BITS)
val X_READ_UNCACHED = UFix(2, TTYPE_BITS)
val X_WRITE_UNCACHED = UFix(3, TTYPE_BITS)
val PTYPE_BITS = 2
val P_INVALIDATE = UFix(0, PTYPE_BITS)
val P_DOWNGRADE = UFix(1, PTYPE_BITS)
val P_COPY = UFix(2, PTYPE_BITS)
// external memory interface // external memory interface
val IMEM_TAG_BITS = 1; val IMEM_TAG_BITS = 1;
val DMEM_TAG_BITS = ceil(log(NMSHR)/log(2)).toInt; val DMEM_TAG_BITS = ceil(log(NMSHR)/log(2)).toInt;