From 18bd0c232b381fcbc70958ed35cd327e754da66a Mon Sep 17 00:00:00 2001
From: Henry Cook <hcook@s144.Millennium.Berkeley.EDU>
Date: Wed, 22 Feb 2012 10:12:13 -0800
Subject: [PATCH] Added coherence message type enums

---
 rocket/src/main/scala/coherence.scala |  8 ++++----
 rocket/src/main/scala/consts.scala    | 11 +++++++++++
 2 files changed, 15 insertions(+), 4 deletions(-)

diff --git a/rocket/src/main/scala/coherence.scala b/rocket/src/main/scala/coherence.scala
index b55ac9a1..9fcf32eb 100644
--- a/rocket/src/main/scala/coherence.scala
+++ b/rocket/src/main/scala/coherence.scala
@@ -4,7 +4,7 @@ import Chisel._
 import Constants._
 
 class TransactionInit extends Bundle {
-  val ttype = Bits(width = 2)
+  val ttype = Bits(width = TTYPE_BITS)
   val tileTransactionID = Bits(width = TILE_XACT_ID_BITS)
   val address = Bits(width = PADDR_BITS)
   val data = Bits(width = MEM_DATA_BITS)
@@ -15,20 +15,20 @@ class TransactionAbort extends Bundle {
 }
 
 class ProbeRequest extends Bundle {
-  val ptype = Bits(width = 2)
+  val ptype = Bits(width = PTYPE_BITS)
   val globalTransactionID = Bits(width = GLOBAL_XACT_ID_BITS)
   val address = Bits(width = PADDR_BITS)
 }
 
 class ProbeReply extends Bundle {
-  val ptype = Bits(width = 2)
+  val ptype = Bits(width = PTYPE_BITS)
   val hasData = Bool()
   val globalTransactionID = Bits(width = GLOBAL_XACT_ID_BITS)
   val data = Bits(width = MEM_DATA_BITS)
 }
 
 class TransactionReply extends Bundle {
-  val ttype = Bits(width = 2)
+  val ttype = Bits(width = TTYPE_BITS)
   val tileTransactionID = Bits(width = TILE_XACT_ID_BITS)
   val globalTransactionID = Bits(width = GLOBAL_XACT_ID_BITS)
   val data = Bits(width = MEM_DATA_BITS)
diff --git a/rocket/src/main/scala/consts.scala b/rocket/src/main/scala/consts.scala
index e00e51cb..34071842 100644
--- a/rocket/src/main/scala/consts.scala
+++ b/rocket/src/main/scala/consts.scala
@@ -177,6 +177,17 @@ object Constants
   val TILE_XACT_ID_BITS = 1; // log2(NMSHR)
   val GLOBAL_XACT_ID_BITS = IDX_BITS; // if one active xact per set
 
+  val TTYPE_BITS = 2
+  val X_READ_SHARED    = UFix(0, TTYPE_BITS)
+  val X_READ_EXCLUSIVE = UFix(1, TTYPE_BITS)
+  val X_READ_UNCACHED  = UFix(2, TTYPE_BITS)
+  val X_WRITE_UNCACHED = UFix(3, TTYPE_BITS)
+
+  val PTYPE_BITS = 2
+  val P_INVALIDATE = UFix(0, PTYPE_BITS)
+  val P_DOWNGRADE  = UFix(1, PTYPE_BITS)
+  val P_COPY       = UFix(2, PTYPE_BITS)
+
   // external memory interface
   val IMEM_TAG_BITS = 1;
   val DMEM_TAG_BITS = ceil(log(NMSHR)/log(2)).toInt;