riscv/rocket-chip
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add default addrMapEntry definition which throws exception

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This commit is contained in:
Howard Mao 2016-08-18 12:29:41 -07:00
parent f7c42499bb
commit 18982d7351
2 changed files with 11 additions and 9 deletions
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17
src/main/scala/Configs.scala
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@ -263,16 +263,17 @@ class WithTestRAM extends Config(
case ExtraDevices => { case ExtraDevices => {
class TestRAMDevice extends Device { class TestRAMDevice extends Device {
val ramSize = 0x1000 val ramSize = 0x1000
def builder(
sPort: Option[ClientUncachedTileLinkIO],
mPort: Option[ClientUncachedTileLinkIO],
extra: Bundle, p: Parameters) {
val testram = Module(new TileLinkTestRAM(ramSize)(p))
testram.io <> sPort.get
}
def addrMapEntry = AddrMapEntry("testram", MemSize(ramSize, MemAttr(AddrMapProt.RW)))
def hasClientPort = false def hasClientPort = false
def hasMMIOPort = true def hasMMIOPort = true
def builder(
mmioPort: Option[ClientUncachedTileLinkIO],
clientPort: Option[ClientUncachedTileLinkIO],
extra: Bundle, p: Parameters) {
val testram = Module(new TileLinkTestRAM(ramSize)(p))
testram.io <> mmioPort.get
}
override def addrMapEntry =
AddrMapEntry("testram", MemSize(ramSize, MemAttr(AddrMapProt.RW)))
} }
Seq(new TestRAMDevice) Seq(new TestRAMDevice)
} }

3
src/main/scala/Devices.scala
View File

@ -15,7 +15,8 @@ abstract class Device {
mmioPort: Option[ClientUncachedTileLinkIO], mmioPort: Option[ClientUncachedTileLinkIO],
clientPort: Option[ClientUncachedTileLinkIO], clientPort: Option[ClientUncachedTileLinkIO],
extra: Bundle, p: Parameters): Unit extra: Bundle, p: Parameters): Unit
def addrMapEntry: AddrMapEntry def addrMapEntry: AddrMapEntry =
throw new UnsupportedOperationException("no addrMapEntry defined")
def makeConfigString(region: MemRegion): String = { def makeConfigString(region: MemRegion): String = {
s"${addrMapEntry.name} {\n" + s"${addrMapEntry.name} {\n" +
s" addr 0x${region.start.toString(16)};\n" + s" addr 0x${region.start.toString(16)};\n" +