From 18982d735120f888799ba57b4e86de6eca3d7529 Mon Sep 17 00:00:00 2001 From: Howard Mao Date: Thu, 18 Aug 2016 12:29:41 -0700 Subject: [PATCH] add default addrMapEntry definition which throws exception --- src/main/scala/Configs.scala | 17 +++++++++-------- src/main/scala/Devices.scala | 3 ++- 2 files changed, 11 insertions(+), 9 deletions(-) diff --git a/src/main/scala/Configs.scala b/src/main/scala/Configs.scala index 698a0737..ac7b621f 100644 --- a/src/main/scala/Configs.scala +++ b/src/main/scala/Configs.scala @@ -263,16 +263,17 @@ class WithTestRAM extends Config( case ExtraDevices => { class TestRAMDevice extends Device { val ramSize = 0x1000 - def builder( - sPort: Option[ClientUncachedTileLinkIO], - mPort: Option[ClientUncachedTileLinkIO], - extra: Bundle, p: Parameters) { - val testram = Module(new TileLinkTestRAM(ramSize)(p)) - testram.io <> sPort.get - } - def addrMapEntry = AddrMapEntry("testram", MemSize(ramSize, MemAttr(AddrMapProt.RW))) def hasClientPort = false def hasMMIOPort = true + def builder( + mmioPort: Option[ClientUncachedTileLinkIO], + clientPort: Option[ClientUncachedTileLinkIO], + extra: Bundle, p: Parameters) { + val testram = Module(new TileLinkTestRAM(ramSize)(p)) + testram.io <> mmioPort.get + } + override def addrMapEntry = + AddrMapEntry("testram", MemSize(ramSize, MemAttr(AddrMapProt.RW))) } Seq(new TestRAMDevice) } diff --git a/src/main/scala/Devices.scala b/src/main/scala/Devices.scala index 0b943958..5c1852d2 100644 --- a/src/main/scala/Devices.scala +++ b/src/main/scala/Devices.scala @@ -15,7 +15,8 @@ abstract class Device { mmioPort: Option[ClientUncachedTileLinkIO], clientPort: Option[ClientUncachedTileLinkIO], extra: Bundle, p: Parameters): Unit - def addrMapEntry: AddrMapEntry + def addrMapEntry: AddrMapEntry = + throw new UnsupportedOperationException("no addrMapEntry defined") def makeConfigString(region: MemRegion): String = { s"${addrMapEntry.name} {\n" + s" addr 0x${region.start.toString(16)};\n" +