riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Get TLB permission checks off D$ clock gating critical path

Browse Source
This commit is contained in:
Andrew Waterman 2017-03-20 01:21:47 -07:00
parent a4164348b4
commit 1875407316
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/main/scala/rocket/DCache.scala
View File

@ -64,7 +64,7 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
val probe_bits = RegEnable(tl_out.b.bits, tl_out.b.fire()) // TODO has data now :(
val s1_nack = Wire(init=Bool(false))
val s1_valid_masked = s1_valid && !io.cpu.s1_kill && !io.cpu.xcpt.asUInt.orR
val s1_valid_not_nacked = s1_valid_masked && !s1_nack
val s1_valid_not_nacked = s1_valid && !s1_nack
val s1_req = Reg(io.cpu.req.bits)
when (metaReadArb.io.out.valid) {
s1_req := io.cpu.req.bits