From 1875407316a0802636dd67d2622eaa8b10a2d296 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Mon, 20 Mar 2017 01:21:47 -0700 Subject: [PATCH] Get TLB permission checks off D$ clock gating critical path --- src/main/scala/rocket/DCache.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/rocket/DCache.scala b/src/main/scala/rocket/DCache.scala index 5504d0c2..88bed70f 100644 --- a/src/main/scala/rocket/DCache.scala +++ b/src/main/scala/rocket/DCache.scala @@ -64,7 +64,7 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) { val probe_bits = RegEnable(tl_out.b.bits, tl_out.b.fire()) // TODO has data now :( val s1_nack = Wire(init=Bool(false)) val s1_valid_masked = s1_valid && !io.cpu.s1_kill && !io.cpu.xcpt.asUInt.orR - val s1_valid_not_nacked = s1_valid_masked && !s1_nack + val s1_valid_not_nacked = s1_valid && !s1_nack val s1_req = Reg(io.cpu.req.bits) when (metaReadArb.io.out.valid) { s1_req := io.cpu.req.bits