riscv/rocket-chip
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rocket: only cache when AcquireT is possible

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This commit is contained in:
Henry Cook
2017-10-10 18:06:58 -07:00
parent 37406706b4
commit 1867a5b226
4 changed files with 7 additions and 8 deletions
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6
src/main/scala/rocket/DCache.scala
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@ -381,7 +381,7 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
val access_address = s2_req.addr
val a_size = mtSize(s2_req.typ)
val a_data = Fill(beatWords, pstore1_data)
val acquire = if (edge.manager.anySupportAcquireB) {
val acquire = if (edge.manager.anySupportAcquireT) {
edge.AcquireBlock(UInt(0), acquire_address, lgCacheBlockBytes, s2_grow_param)._2 // Cacheability checked by tlb
} else {
Wire(new TLBundleA(edge.bundle))
@ -583,7 +583,7 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
when (releaseDone) { release_state := s_probe_write_meta }
}
when (release_state.isOneOf(s_voluntary_writeback, s_voluntary_write_meta)) {
if (edge.manager.anySupportAcquireB)
if (edge.manager.anySupportAcquireT)
tl_out_c.bits := edge.Release(fromSource = 0.U,
toAddress = 0.U,
lgSize = lgCacheBlockBytes,
@ -696,7 +696,7 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
metaArb.io.in(5).bits.way_en := ~UInt(0, nWays)
metaArb.io.in(5).bits.data := metaArb.io.in(4).bits.data
// Only flush D$ on FENCE.I if some cached executable regions are untracked.
if (!edge.manager.managers.forall(m => !m.supportsAcquireB || !m.executable || m.regionType >= RegionType.TRACKED)) {
if (!edge.manager.managers.forall(m => !m.supportsAcquireT || !m.executable || m.regionType >= RegionType.TRACKED)) {
when (tl_out_a.fire() && !s2_uncached) { flushed := false }
when (flushing) {
s1_victim_way := flushCounter >> log2Up(nSets)