From 1867a5b226f29604f4c724d664cac18f485fb51f Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Tue, 10 Oct 2017 18:06:58 -0700 Subject: [PATCH] rocket: only cache when AcquireT is possible --- src/main/scala/rocket/DCache.scala | 6 +++--- src/main/scala/rocket/TLB.scala | 2 +- src/main/scala/rocket/TLBPermissions.scala | 1 - src/main/scala/tilelink/CacheCork.scala | 6 +++--- 4 files changed, 7 insertions(+), 8 deletions(-) diff --git a/src/main/scala/rocket/DCache.scala b/src/main/scala/rocket/DCache.scala index ed872a2a..db5cd49e 100644 --- a/src/main/scala/rocket/DCache.scala +++ b/src/main/scala/rocket/DCache.scala @@ -381,7 +381,7 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) { val access_address = s2_req.addr val a_size = mtSize(s2_req.typ) val a_data = Fill(beatWords, pstore1_data) - val acquire = if (edge.manager.anySupportAcquireB) { + val acquire = if (edge.manager.anySupportAcquireT) { edge.AcquireBlock(UInt(0), acquire_address, lgCacheBlockBytes, s2_grow_param)._2 // Cacheability checked by tlb } else { Wire(new TLBundleA(edge.bundle)) @@ -583,7 +583,7 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) { when (releaseDone) { release_state := s_probe_write_meta } } when (release_state.isOneOf(s_voluntary_writeback, s_voluntary_write_meta)) { - if (edge.manager.anySupportAcquireB) + if (edge.manager.anySupportAcquireT) tl_out_c.bits := edge.Release(fromSource = 0.U, toAddress = 0.U, lgSize = lgCacheBlockBytes, @@ -696,7 +696,7 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) { metaArb.io.in(5).bits.way_en := ~UInt(0, nWays) metaArb.io.in(5).bits.data := metaArb.io.in(4).bits.data // Only flush D$ on FENCE.I if some cached executable regions are untracked. - if (!edge.manager.managers.forall(m => !m.supportsAcquireB || !m.executable || m.regionType >= RegionType.TRACKED)) { + if (!edge.manager.managers.forall(m => !m.supportsAcquireT || !m.executable || m.regionType >= RegionType.TRACKED)) { when (tl_out_a.fire() && !s2_uncached) { flushed := false } when (flushing) { s1_victim_way := flushCounter >> log2Up(nSets) diff --git a/src/main/scala/rocket/TLB.scala b/src/main/scala/rocket/TLB.scala index 47619484..4b6f72fe 100644 --- a/src/main/scala/rocket/TLB.scala +++ b/src/main/scala/rocket/TLB.scala @@ -112,7 +112,7 @@ class TLB(instruction: Boolean, lgMaxSize: Int, nEntries: Int)(implicit edge: TL val legal_address = edge.manager.findSafe(mpu_physaddr).reduce(_||_) def fastCheck(member: TLManagerParameters => Boolean) = legal_address && edge.manager.fastProperty(mpu_physaddr, member, (b:Boolean) => Bool(b)) - val cacheable = fastCheck(_.supportsAcquireB) && (instruction || !usingDataScratchpad) + val cacheable = fastCheck(_.supportsAcquireT) && (instruction || !usingDataScratchpad) val homogeneous = TLBPageLookup(edge.manager.managers, xLen, p(CacheBlockBytes), BigInt(1) << pgIdxBits)(mpu_physaddr).homogeneous val prot_r = fastCheck(_.supportsGet) && pmp.io.r val prot_w = fastCheck(_.supportsPutFull) && pmp.io.w diff --git a/src/main/scala/rocket/TLBPermissions.scala b/src/main/scala/rocket/TLBPermissions.scala index b9cfb430..7196aff3 100644 --- a/src/main/scala/rocket/TLBPermissions.scala +++ b/src/main/scala/rocket/TLBPermissions.scala @@ -46,7 +46,6 @@ object TLBPageLookup require (!m.supportsAcquireT || m.supportsAcquireT .contains(xferSizes), s"MemoryMap region ${m.name} only supports ${m.supportsAcquireT} AcquireT, but must support ${xferSizes}") require (!m.supportsLogical || m.supportsLogical .contains(amoSizes), s"MemoryMap region ${m.name} only supports ${m.supportsLogical} Logical, but must support ${amoSizes}") require (!m.supportsArithmetic || m.supportsArithmetic.contains(amoSizes), s"MemoryMap region ${m.name} only supports ${m.supportsArithmetic} Arithmetic, but must support ${amoSizes}") - require (m.supportsAcquireT || !m.supportsAcquireB, s"MemoryMap region ${m.name} supports AcquireB (cached read) but not AcquireT (cached write)... and rocket assumes this") (m.address, TLBFixedPermissions( e = Seq(RegionType.PUT_EFFECTS, RegionType.GET_EFFECTS) contains m.regionType, diff --git a/src/main/scala/tilelink/CacheCork.scala b/src/main/scala/tilelink/CacheCork.scala index 5307d7e9..063c58a4 100644 --- a/src/main/scala/tilelink/CacheCork.scala +++ b/src/main/scala/tilelink/CacheCork.scala @@ -19,9 +19,9 @@ class TLCacheCork(unsafe: Boolean = false)(implicit p: Parameters) extends LazyM managerFn = { case mp => mp.copy( endSinkId = 1, - managers = mp.managers.map { m => m.copy( // Rocket requires m.supportsAcquireT || !m.supportsAcquireB, so, don't cache ROMs - supportsAcquireB = if (m.regionType == RegionType.UNCACHED && m.supportsPutFull) m.supportsGet else m.supportsAcquireB, - supportsAcquireT = if (m.regionType == RegionType.UNCACHED) m.supportsPutFull else m.supportsAcquireT)})}) + managers = mp.managers.map { m => m.copy( + supportsAcquireB = if (m.regionType == RegionType.UNCACHED) m.supportsGet else m.supportsAcquireB, + supportsAcquireT = if (m.regionType == RegionType.UNCACHED) m.supportsPutFull else m.supportsAcquireT)})}) lazy val module = new LazyModuleImp(this) { (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>