Use stop() to exit cleanly
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0967f3cfed
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@ -358,12 +358,12 @@ class ComparatorTile(resetSignal: Bool)(implicit val p: Parameters) extends Tile
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require (nUncachedTileLinkPorts == nTargets + 1)
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val core = Module(new ComparatorCore)
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val finisher = Module(new GroundTestFinisher)
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// Connect 0..nTargets-1 to core
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(io.uncached zip core.io.uncached) map { case (u, c) => u <> c }
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io.uncached(nTargets) <> finisher.io.mem
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finisher.io.finished := core.io.finished
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when (core.io.finished) {
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stop()
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}
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// Work-around cachedClients must be >= 1 issue
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io.cached(0).acquire.valid := Bool(false)
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@ -104,33 +104,6 @@ abstract class GroundTest(implicit val p: Parameters) extends Module
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val io = new GroundTestIO
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}
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class GroundTestFinisher(implicit p: Parameters) extends TLModule()(p) {
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val io = new Bundle {
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val finished = Bool(INPUT)
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val mem = new ClientUncachedTileLinkIO
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}
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val addrBits = p(PAddrBits)
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val offsetBits = tlBeatAddrBits + tlByteAddrBits
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val tohostAddr = UInt(p(TohostAddr), addrBits)
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val s_idle :: s_write :: s_wait :: s_done :: Nil = Enum(Bits(), 4)
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val state = Reg(init = s_idle)
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when (state === s_idle && io.finished) { state := s_write }
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when (io.mem.acquire.fire()) { state := s_wait }
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when (io.mem.grant.fire()) { state := s_done }
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io.mem.acquire.valid := (state === s_write)
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io.mem.acquire.bits := Put(
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client_xact_id = UInt(0),
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addr_block = tohostAddr(addrBits - 1, offsetBits),
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addr_beat = tohostAddr(offsetBits - 1, tlByteAddrBits),
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data = UInt(1),
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wmask = SInt(-1, 8).asUInt)
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io.mem.grant.ready := (state === s_wait)
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}
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class GroundTestTile(id: Int, resetSignal: Bool)
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(implicit val p: Parameters)
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extends Tile(resetSignal = resetSignal)(p)
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@ -165,9 +138,9 @@ class GroundTestTile(id: Int, resetSignal: Bool)
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// Only Tile 0 needs to write tohost
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if (id == 0) {
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val finisher = Module(new GroundTestFinisher)
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finisher.io.finished := test.io.finished
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memPorts += finisher.io.mem
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when (test.io.finished) {
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stop()
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}
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}
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if (ptwPorts.size > 0) {
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