From 1844bac5bc4e5dbfc5d696a5a2d07819e674c86d Mon Sep 17 00:00:00 2001
From: Andrew Waterman <waterman@cs.berkeley.edu>
Date: Thu, 23 Jun 2016 12:16:37 -0700
Subject: [PATCH] Use stop() to exit cleanly

---
 groundtest/src/main/scala/comparator.scala |  6 ++--
 groundtest/src/main/scala/tile.scala       | 33 ++--------------------
 2 files changed, 6 insertions(+), 33 deletions(-)

diff --git a/groundtest/src/main/scala/comparator.scala b/groundtest/src/main/scala/comparator.scala
index a6f78b55..a3981f4f 100644
--- a/groundtest/src/main/scala/comparator.scala
+++ b/groundtest/src/main/scala/comparator.scala
@@ -358,12 +358,12 @@ class ComparatorTile(resetSignal: Bool)(implicit val p: Parameters) extends Tile
   require (nUncachedTileLinkPorts == nTargets + 1)
   
   val core = Module(new ComparatorCore)
-  val finisher = Module(new GroundTestFinisher)
   
   // Connect 0..nTargets-1 to core
   (io.uncached zip core.io.uncached) map { case (u, c) => u <> c }
-  io.uncached(nTargets) <> finisher.io.mem
-  finisher.io.finished := core.io.finished
+  when (core.io.finished) {
+    stop()
+  }
   
   // Work-around cachedClients must be >= 1 issue
   io.cached(0).acquire.valid   := Bool(false)
diff --git a/groundtest/src/main/scala/tile.scala b/groundtest/src/main/scala/tile.scala
index 31d7579e..f23bc2d6 100644
--- a/groundtest/src/main/scala/tile.scala
+++ b/groundtest/src/main/scala/tile.scala
@@ -104,33 +104,6 @@ abstract class GroundTest(implicit val p: Parameters) extends Module
   val io = new GroundTestIO
 }
 
-class GroundTestFinisher(implicit p: Parameters) extends TLModule()(p) {
-  val io = new Bundle {
-    val finished = Bool(INPUT)
-    val mem = new ClientUncachedTileLinkIO
-  }
-
-  val addrBits = p(PAddrBits)
-  val offsetBits = tlBeatAddrBits + tlByteAddrBits
-  val tohostAddr = UInt(p(TohostAddr), addrBits)
-
-  val s_idle :: s_write :: s_wait :: s_done :: Nil = Enum(Bits(), 4)
-  val state = Reg(init = s_idle)
-
-  when (state === s_idle && io.finished) { state := s_write }
-  when (io.mem.acquire.fire()) { state := s_wait }
-  when (io.mem.grant.fire()) { state := s_done }
-
-  io.mem.acquire.valid := (state === s_write)
-  io.mem.acquire.bits := Put(
-    client_xact_id = UInt(0),
-    addr_block = tohostAddr(addrBits - 1, offsetBits),
-    addr_beat = tohostAddr(offsetBits - 1, tlByteAddrBits),
-    data = UInt(1),
-    wmask = SInt(-1, 8).asUInt)
-  io.mem.grant.ready := (state === s_wait)
-}
-
 class GroundTestTile(id: Int, resetSignal: Bool)
                     (implicit val p: Parameters)
                     extends Tile(resetSignal = resetSignal)(p)
@@ -165,9 +138,9 @@ class GroundTestTile(id: Int, resetSignal: Bool)
 
   // Only Tile 0 needs to write tohost
   if (id == 0) {
-    val finisher = Module(new GroundTestFinisher)
-    finisher.io.finished := test.io.finished
-    memPorts += finisher.io.mem
+    when (test.io.finished) {
+      stop()
+    }
   }
 
   if (ptwPorts.size > 0) {