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Use stop() to exit cleanly

This commit is contained in:
Andrew Waterman 2016-06-23 12:16:37 -07:00
parent 0967f3cfed
commit 1844bac5bc
2 changed files with 6 additions and 33 deletions

View File

@ -358,12 +358,12 @@ class ComparatorTile(resetSignal: Bool)(implicit val p: Parameters) extends Tile
require (nUncachedTileLinkPorts == nTargets + 1) require (nUncachedTileLinkPorts == nTargets + 1)
val core = Module(new ComparatorCore) val core = Module(new ComparatorCore)
val finisher = Module(new GroundTestFinisher)
// Connect 0..nTargets-1 to core // Connect 0..nTargets-1 to core
(io.uncached zip core.io.uncached) map { case (u, c) => u <> c } (io.uncached zip core.io.uncached) map { case (u, c) => u <> c }
io.uncached(nTargets) <> finisher.io.mem when (core.io.finished) {
finisher.io.finished := core.io.finished stop()
}
// Work-around cachedClients must be >= 1 issue // Work-around cachedClients must be >= 1 issue
io.cached(0).acquire.valid := Bool(false) io.cached(0).acquire.valid := Bool(false)

View File

@ -104,33 +104,6 @@ abstract class GroundTest(implicit val p: Parameters) extends Module
val io = new GroundTestIO val io = new GroundTestIO
} }
class GroundTestFinisher(implicit p: Parameters) extends TLModule()(p) {
val io = new Bundle {
val finished = Bool(INPUT)
val mem = new ClientUncachedTileLinkIO
}
val addrBits = p(PAddrBits)
val offsetBits = tlBeatAddrBits + tlByteAddrBits
val tohostAddr = UInt(p(TohostAddr), addrBits)
val s_idle :: s_write :: s_wait :: s_done :: Nil = Enum(Bits(), 4)
val state = Reg(init = s_idle)
when (state === s_idle && io.finished) { state := s_write }
when (io.mem.acquire.fire()) { state := s_wait }
when (io.mem.grant.fire()) { state := s_done }
io.mem.acquire.valid := (state === s_write)
io.mem.acquire.bits := Put(
client_xact_id = UInt(0),
addr_block = tohostAddr(addrBits - 1, offsetBits),
addr_beat = tohostAddr(offsetBits - 1, tlByteAddrBits),
data = UInt(1),
wmask = SInt(-1, 8).asUInt)
io.mem.grant.ready := (state === s_wait)
}
class GroundTestTile(id: Int, resetSignal: Bool) class GroundTestTile(id: Int, resetSignal: Bool)
(implicit val p: Parameters) (implicit val p: Parameters)
extends Tile(resetSignal = resetSignal)(p) extends Tile(resetSignal = resetSignal)(p)
@ -165,9 +138,9 @@ class GroundTestTile(id: Int, resetSignal: Bool)
// Only Tile 0 needs to write tohost // Only Tile 0 needs to write tohost
if (id == 0) { if (id == 0) {
val finisher = Module(new GroundTestFinisher) when (test.io.finished) {
finisher.io.finished := test.io.finished stop()
memPorts += finisher.io.mem }
} }
if (ptwPorts.size > 0) { if (ptwPorts.size > 0) {