riscv/rocket-chip
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Expanded front-end to support superscalar fetch.

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This commit is contained in:
Christopher Celio
2014-09-17 14:24:03 -07:00
parent 238f7761f6
commit 180d3d365d
4 changed files with 35 additions and 10 deletions
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25
rocket/src/main/scala/icache.scala
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@ -1,5 +1,3 @@
// See LICENSE for license details.
package rocket
import Chisel._
@ -24,7 +22,8 @@ class FrontendReq extends CoreBundle {
class FrontendResp extends CoreBundle {
val pc = UInt(width = params(VAddrBits)+1) // ID stage PC
val data = Bits(width = coreInstBits)
val data = Vec.fill(coreFetchWidth) (Bits(width = coreInstBits))
val mask = Bits(width = coreFetchWidth)
val xcpt_ma = Bool()
val xcpt_if = Bool()
}
@ -60,12 +59,12 @@ class Frontend extends FrontendModule
val msb = vaddrBits-1
val btbTarget = Cat(btb.io.resp.bits.target(msb), btb.io.resp.bits.target)
val pcp4_0 = s1_pc + UInt(coreInstBytes)
val pcp4 = Cat(s1_pc(msb) & pcp4_0(msb), pcp4_0(msb,0))
val ntpc_0 = s1_pc + UInt(coreInstBytes)
val ntpc = Cat(s1_pc(msb) & ntpc_0(msb), ntpc_0(msb,0))
val icmiss = s2_valid && !icache.io.resp.valid
val predicted_npc = Mux(btb.io.resp.bits.taken, btbTarget, pcp4)
val predicted_npc = Mux(btb.io.resp.bits.taken, btbTarget, ntpc)
val npc = Mux(icmiss, s2_pc, predicted_npc).toUInt
val s0_same_block = !icmiss && !io.cpu.req.valid && !btb.io.resp.bits.taken && ((pcp4 & rowBytes) === (s1_pc & rowBytes))
val s0_same_block = !icmiss && !io.cpu.req.valid && !btb.io.resp.bits.taken && ((ntpc & rowBytes) === (s1_pc & rowBytes))
val stall = io.cpu.resp.valid && !io.cpu.resp.ready
when (!stall) {
@ -106,7 +105,17 @@ class Frontend extends FrontendModule
io.cpu.resp.valid := s2_valid && (s2_xcpt_if || icache.io.resp.valid)
io.cpu.resp.bits.pc := s2_pc & SInt(-coreInstBytes) // discard PC LSBs
io.cpu.resp.bits.data := icache.io.resp.bits.datablock >> (s2_pc(log2Up(rowBytes)-1,log2Up(coreInstBytes)) << log2Up(coreInstBits))
val fetch_data = icache.io.resp.bits.datablock >> (s2_pc(log2Up(rowBytes)-1,log2Up(coreFetchWidth*coreInstBytes)) << log2Up(coreFetchWidth*coreInstBits))
for (i <- 0 until coreFetchWidth) {
io.cpu.resp.bits.data(i) := fetch_data(i*coreInstBits+coreInstBits-1, i*coreInstBits)
}
val all_ones = UInt((1 << coreFetchWidth)-1)
val msk_pc = all_ones << s2_pc(log2Up(coreFetchWidth)-1+2,2)
io.cpu.resp.bits.mask := msk_pc & btb.io.resp.bits.mask
io.cpu.resp.bits.xcpt_ma := s2_pc(log2Up(coreInstBytes)-1,0) != UInt(0)
io.cpu.resp.bits.xcpt_if := s2_xcpt_if