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coreplex: name LazyModules

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This commit is contained in:
Wesley W. Terpstra 2017-09-12 12:16:28 -07:00
parent 1fedabcb55
commit 17ba209ed0
2 changed files with 16 additions and 5 deletions
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13
src/main/scala/coreplex/Configs.scala
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@ -185,14 +185,21 @@ class WithRoccExample extends Config((site, here, up) => {
Seq( Seq(
RoCCParams( RoCCParams(
opcodes = OpcodeSet.custom0, opcodes = OpcodeSet.custom0,
generator = (p: Parameters) => LazyModule(new AccumulatorExample()(p))), generator = (p: Parameters) => {
val accumulator = LazyModule(new AccumulatorExample()(p))
accumulator}),
RoCCParams( RoCCParams(
opcodes = OpcodeSet.custom1, opcodes = OpcodeSet.custom1,
generator = (p: Parameters) => LazyModule(new TranslatorExample()(p)), generator = (p: Parameters) => {
val translator = LazyModule(new TranslatorExample()(p))
translator},
nPTWPorts = 1), nPTWPorts = 1),
RoCCParams( RoCCParams(
opcodes = OpcodeSet.custom2, opcodes = OpcodeSet.custom2,
generator = (p: Parameters) => LazyModule(new CharacterCountExample()(p))) generator = (p: Parameters) => {
val counter = LazyModule(new CharacterCountExample()(p))
counter
})
)) ))
} }
}) })

8
src/main/scala/coreplex/Ports.scala
View File

@ -69,7 +69,10 @@ trait HasMasterAXI4MemPortBundle {
val mem_axi4: HeterogeneousBag[AXI4Bundle] val mem_axi4: HeterogeneousBag[AXI4Bundle]
val nMemoryChannels: Int val nMemoryChannels: Int
def connectSimAXIMem(dummy: Int = 1) = { def connectSimAXIMem(dummy: Int = 1) = {
if (nMemoryChannels > 0) Module(LazyModule(new SimAXIMem(nMemoryChannels)).module).io.axi4 <> mem_axi4 if (nMemoryChannels > 0) {
val mem = LazyModule(new SimAXIMem(nMemoryChannels))
Module(mem.module).io.axi4 <> mem_axi4
}
} }
} }
@ -107,7 +110,8 @@ trait HasMasterAXI4MMIOPortBundle {
implicit val p: Parameters implicit val p: Parameters
val mmio_axi4: HeterogeneousBag[AXI4Bundle] val mmio_axi4: HeterogeneousBag[AXI4Bundle]
def connectSimAXIMMIO(dummy: Int = 1) { def connectSimAXIMMIO(dummy: Int = 1) {
Module(LazyModule(new SimAXIMem(1, 4096)).module).io.axi4 <> mmio_axi4 val mmio_mem = LazyModule(new SimAXIMem(1, 4096))
Module(mmio_mem.module).io.axi4 <> mmio_axi4
} }
} }