diff --git a/src/main/scala/coreplex/Configs.scala b/src/main/scala/coreplex/Configs.scala
index 46865cde..563f6f85 100644
--- a/src/main/scala/coreplex/Configs.scala
+++ b/src/main/scala/coreplex/Configs.scala
@@ -185,14 +185,21 @@ class WithRoccExample extends Config((site, here, up) => {
       Seq(
         RoCCParams(
           opcodes = OpcodeSet.custom0,
-          generator = (p: Parameters) => LazyModule(new AccumulatorExample()(p))),
+          generator = (p: Parameters) => {
+            val accumulator = LazyModule(new AccumulatorExample()(p))
+            accumulator}),
         RoCCParams(
           opcodes = OpcodeSet.custom1,
-          generator = (p: Parameters) => LazyModule(new TranslatorExample()(p)),
+          generator = (p: Parameters) => {
+            val translator = LazyModule(new TranslatorExample()(p))
+            translator},
           nPTWPorts = 1),
         RoCCParams(
           opcodes = OpcodeSet.custom2,
-          generator = (p: Parameters) => LazyModule(new CharacterCountExample()(p)))
+          generator = (p: Parameters) => {
+            val counter = LazyModule(new CharacterCountExample()(p))
+            counter
+          })
         ))
     }
 })
diff --git a/src/main/scala/coreplex/Ports.scala b/src/main/scala/coreplex/Ports.scala
index 4af44050..f1c1ae53 100644
--- a/src/main/scala/coreplex/Ports.scala
+++ b/src/main/scala/coreplex/Ports.scala
@@ -69,7 +69,10 @@ trait HasMasterAXI4MemPortBundle {
   val mem_axi4: HeterogeneousBag[AXI4Bundle]
   val nMemoryChannels: Int
   def connectSimAXIMem(dummy: Int = 1) = {
-    if (nMemoryChannels > 0) Module(LazyModule(new SimAXIMem(nMemoryChannels)).module).io.axi4 <> mem_axi4
+    if (nMemoryChannels > 0)  {
+      val mem = LazyModule(new SimAXIMem(nMemoryChannels))
+      Module(mem.module).io.axi4 <> mem_axi4
+    }
   }
 }
 
@@ -107,7 +110,8 @@ trait HasMasterAXI4MMIOPortBundle {
   implicit val p: Parameters
   val mmio_axi4: HeterogeneousBag[AXI4Bundle]
   def connectSimAXIMMIO(dummy: Int = 1) {
-    Module(LazyModule(new SimAXIMem(1, 4096)).module).io.axi4 <> mmio_axi4
+    val mmio_mem = LazyModule(new SimAXIMem(1, 4096))
+    Module(mmio_mem.module).io.axi4 <> mmio_axi4
   }
 }