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htif parameters trait

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This commit is contained in:
Henry Cook 2014-08-24 19:27:58 -07:00
parent dc5643b12f
commit 17b2359c9a
1 changed files with 24 additions and 21 deletions
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45
uncore/src/main/scala/htif.scala
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@ -9,7 +9,18 @@ case object HTIFNSCR extends Field[Int]
case object HTIFOffsetBits extends Field[Int] case object HTIFOffsetBits extends Field[Int]
case object HTIFNCores extends Field[Int] case object HTIFNCores extends Field[Int]
class HostIO(val w: Int) extends Bundle abstract trait HTIFParameters extends UsesParameters {
val dataBits = params(TLDataBits)
val co = params(TLCoherence)
val w = params(HTIFWidth)
val nSCR = params(HTIFNSCR)
val offsetBits = params(HTIFOffsetBits)
val nCores = params(HTIFNCores)
}
abstract class HTIFBundle extends Bundle with HTIFParameters
class HostIO extends HTIFBundle
{ {
val clk = Bool(OUTPUT) val clk = Bool(OUTPUT)
val clk_edge = Bool(OUTPUT) val clk_edge = Bool(OUTPUT)
@ -25,42 +36,34 @@ class PCRReq extends Bundle
val data = Bits(width = 64) val data = Bits(width = 64)
} }
class HTIFIO extends Bundle class HTIFIO extends HTIFBundle {
{
val reset = Bool(INPUT) val reset = Bool(INPUT)
val id = UInt(INPUT, log2Up(params(HTIFNCores))) val id = UInt(INPUT, log2Up(nCores))
val pcr_req = Decoupled(new PCRReq).flip val pcr_req = Decoupled(new PCRReq).flip
val pcr_rep = Decoupled(Bits(width = 64)) val pcr_rep = Decoupled(Bits(width = 64))
val ipi_req = Decoupled(Bits(width = log2Up(params(HTIFNCores)))) val ipi_req = Decoupled(Bits(width = log2Up(nCores)))
val ipi_rep = Decoupled(Bool()).flip val ipi_rep = Decoupled(Bool()).flip
val debug_stats_pcr = Bool(OUTPUT) val debug_stats_pcr = Bool(OUTPUT)
// wired directly to stats register // wired directly to stats register
// expected to be used to quickly indicate to testbench to do logging b/c in 'interesting' work // expected to be used to quickly indicate to testbench to do logging b/c in 'interesting' work
} }
class SCRIO extends Bundle class SCRIO extends HTIFBundle {
{ val rdata = Vec.fill(nSCR){Bits(INPUT, 64)}
val rdata = Vec.fill(params(HTIFNSCR)){Bits(INPUT, 64)}
val wen = Bool(OUTPUT) val wen = Bool(OUTPUT)
val waddr = UInt(OUTPUT, log2Up(params(HTIFNSCR))) val waddr = UInt(OUTPUT, log2Up(nSCR))
val wdata = Bits(OUTPUT, 64) val wdata = Bits(OUTPUT, 64)
} }
class HTIF(pcr_RESET: Int) extends Module class HTIFModuleIO extends HTIFBundle {
{ val host = new HostIO
val dataBits = params(TLDataBits) val cpu = Vec.fill(nCores){new HTIFIO}.flip
val co = params(TLCoherence)
val w = params(HTIFWidth)
val nSCR = params(HTIFNSCR)
val offsetBits = params(HTIFOffsetBits)
val nCores = params(HTIFNCores)
val io = new Bundle {
val host = new HostIO(w)
val cpu = Vec.fill(nCores){new HTIFIO().flip}
val mem = new TileLinkIO val mem = new TileLinkIO
val scr = new SCRIO val scr = new SCRIO
} }
class HTIF(pcr_RESET: Int) extends Module with HTIFParameters {
val io = new HTIFModuleIO
io.host.debug_stats_pcr := io.cpu.map(_.debug_stats_pcr).reduce(_||_) io.host.debug_stats_pcr := io.cpu.map(_.debug_stats_pcr).reduce(_||_)
// system is 'interesting' if any tile is 'interesting' // system is 'interesting' if any tile is 'interesting'