htif parameters trait
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@ -9,7 +9,18 @@ case object HTIFNSCR extends Field[Int]
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case object HTIFOffsetBits extends Field[Int]
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case object HTIFOffsetBits extends Field[Int]
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case object HTIFNCores extends Field[Int]
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case object HTIFNCores extends Field[Int]
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class HostIO(val w: Int) extends Bundle
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abstract trait HTIFParameters extends UsesParameters {
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val dataBits = params(TLDataBits)
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val co = params(TLCoherence)
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val w = params(HTIFWidth)
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val nSCR = params(HTIFNSCR)
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val offsetBits = params(HTIFOffsetBits)
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val nCores = params(HTIFNCores)
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}
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abstract class HTIFBundle extends Bundle with HTIFParameters
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class HostIO extends HTIFBundle
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{
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{
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val clk = Bool(OUTPUT)
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val clk = Bool(OUTPUT)
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val clk_edge = Bool(OUTPUT)
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val clk_edge = Bool(OUTPUT)
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@ -25,42 +36,34 @@ class PCRReq extends Bundle
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val data = Bits(width = 64)
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val data = Bits(width = 64)
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}
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}
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class HTIFIO extends Bundle
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class HTIFIO extends HTIFBundle {
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{
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val reset = Bool(INPUT)
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val reset = Bool(INPUT)
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val id = UInt(INPUT, log2Up(params(HTIFNCores)))
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val id = UInt(INPUT, log2Up(nCores))
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val pcr_req = Decoupled(new PCRReq).flip
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val pcr_req = Decoupled(new PCRReq).flip
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val pcr_rep = Decoupled(Bits(width = 64))
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val pcr_rep = Decoupled(Bits(width = 64))
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val ipi_req = Decoupled(Bits(width = log2Up(params(HTIFNCores))))
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val ipi_req = Decoupled(Bits(width = log2Up(nCores)))
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val ipi_rep = Decoupled(Bool()).flip
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val ipi_rep = Decoupled(Bool()).flip
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val debug_stats_pcr = Bool(OUTPUT)
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val debug_stats_pcr = Bool(OUTPUT)
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// wired directly to stats register
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// wired directly to stats register
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// expected to be used to quickly indicate to testbench to do logging b/c in 'interesting' work
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// expected to be used to quickly indicate to testbench to do logging b/c in 'interesting' work
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}
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}
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class SCRIO extends Bundle
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class SCRIO extends HTIFBundle {
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{
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val rdata = Vec.fill(nSCR){Bits(INPUT, 64)}
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val rdata = Vec.fill(params(HTIFNSCR)){Bits(INPUT, 64)}
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val wen = Bool(OUTPUT)
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val wen = Bool(OUTPUT)
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val waddr = UInt(OUTPUT, log2Up(params(HTIFNSCR)))
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val waddr = UInt(OUTPUT, log2Up(nSCR))
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val wdata = Bits(OUTPUT, 64)
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val wdata = Bits(OUTPUT, 64)
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}
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}
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class HTIF(pcr_RESET: Int) extends Module
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class HTIFModuleIO extends HTIFBundle {
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{
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val host = new HostIO
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val dataBits = params(TLDataBits)
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val cpu = Vec.fill(nCores){new HTIFIO}.flip
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val co = params(TLCoherence)
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val w = params(HTIFWidth)
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val nSCR = params(HTIFNSCR)
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val offsetBits = params(HTIFOffsetBits)
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val nCores = params(HTIFNCores)
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val io = new Bundle {
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val host = new HostIO(w)
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val cpu = Vec.fill(nCores){new HTIFIO().flip}
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val mem = new TileLinkIO
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val mem = new TileLinkIO
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val scr = new SCRIO
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val scr = new SCRIO
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}
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}
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class HTIF(pcr_RESET: Int) extends Module with HTIFParameters {
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val io = new HTIFModuleIO
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io.host.debug_stats_pcr := io.cpu.map(_.debug_stats_pcr).reduce(_||_)
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io.host.debug_stats_pcr := io.cpu.map(_.debug_stats_pcr).reduce(_||_)
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// system is 'interesting' if any tile is 'interesting'
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// system is 'interesting' if any tile is 'interesting'
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